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194 条记录 (耗时 0.045 秒)

    Circuit having source follower and semiconductor device having the circuit
    51.
    发明授权
    Circuit having source follower and semiconductor device having the circuit 有权
    具有源极跟随器和具有该电路的半导体器件的电路

    公开(公告)号：US07595794B2

    公开(公告)日：2009-09-29

    申请号：US11474938

    申请日：2006-06-27

    申请人： Hiroyuki Miyake ,  Yutaka Shionoiri

    发明人： Hiroyuki Miyake ,  Yutaka Shionoiri

    IPC分类号： G06F3/038 ,  G09G5/00

    CPC分类号： G09G3/20 ,  G09G2310/0275 ,  H03F1/301 ,  H03F3/505

    摘要： When a potential of a power supply line varies according to a flowing current, the gate-source voltage Vgs of a transistor also varies, leading to variations in the constant current between each source follower. In order to solve this problem, a potential Vb of the gate terminal of a transistor as a constant current source is changed in the same manner as a power supply line Vss which is connected to the source terminal of the transistor. Therefore, variations in the constant current are suppressed and variations in the output of the source followers are thus suppressed. In addition, by connecting the circuit having source followers to the output side of a signal line driver circuit, it can be prevented that luminance unevenness of a striped pattern is recognized in a display portion of a semiconductor device.

    摘要翻译： 当电源线的电位根据流动电流而变化时，晶体管的栅极 - 源极电压Vgs也变化，导致每个源极跟随器之间的恒定电流的变化。 为了解决这个问题，作为恒流源的晶体管的栅极端子的电势Vb以与连接到晶体管的源极端子的电源线Vss相同的方式改变。 因此，抑制恒定电流的变化，从而抑制源极跟随器的输出的变化。 此外，通过将具有源极跟随器的电路连接到信号线驱动电路的输出侧，可以防止在半导体器件的显示部分中识别出条纹图案的亮度不均匀。

    Source follower, voltage follower, and semiconductor device
    52.
    发明授权
    Source follower, voltage follower, and semiconductor device 有权
    源极跟随器，电压跟随器和半导体器件

    公开(公告)号：US07307463B2

    公开(公告)日：2007-12-11

    申请号：US10815775

    申请日：2004-04-02

    申请人： Hiroyuki Miyake ,  Yutaka Shionoiri

    发明人： Hiroyuki Miyake ,  Yutaka Shionoiri

    IPC分类号： H03K5/153 ,  G09G3/36

    CPC分类号： G11C19/28 ,  G09G3/3685 ,  G09G2310/0275 ,  G11C19/00 ,  G11C19/184 ,  H03F3/505

    摘要： A source follower in which any one of the following three modes is selected by a plurality of switching elements: a first mode in which a first potential is supplied to a gate of a transistor and an input potential is supplied to a first electrode of a capacitor respectively and a second electrode of the capacitor and a source of the transistor are connected, a second mode in which an input potential is supplied to the first electrode and the gate of the transistor and the second electrode floats, and a third mode in which the first electrode and the gate of the transistor are connected and a potential thereof floats and a second potential is supplied to the second electrode, a drain of the transistor is supplied with a third potential, and a potential of the source of the transistor is supplied to a subsequent circuit.

    摘要翻译： 源跟随器，其中以下三种模式中的任何一种由多个开关元件选择：第一模式，其中第一电位被提供给晶体管的栅极并且输入电位被提供给电容器的第一电极 分别连接电容器的第二电极和晶体管的源极，其中输入电位被提供给第一电极并且晶体管和第二电极的栅极浮置的第二模式以及第三模式，其中 第一电极和晶体管的栅极连接，并且其电位浮动，并且第二电位被提供给第二电极，晶体管的漏极被提供第三电位，并且将晶体管的源极的电位供给到 一个后续的电路。

    Liquid crystal display device and method of driving a liquid crystal display device
    53.
    发明授权
    Liquid crystal display device and method of driving a liquid crystal display device 失效
    液晶显示装置及驱动液晶显示装置的方法

    公开(公告)号：US07268756B2

    公开(公告)日：2007-09-11

    申请号：US10650930

    申请日：2003-08-29

    申请人： Jun Koyama ,  Yutaka Shionoiri ,  Hiroyuki Miyake ,  Yasuhiro Hirayama ,  Buyeol Lee

    发明人： Jun Koyama ,  Yutaka Shionoiri ,  Hiroyuki Miyake ,  Yasuhiro Hirayama ,  Buyeol Lee

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3688 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0297 ,  G09G2320/0233

    摘要： A liquid crystal display device having analog buffer circuits, which is reduced in luminance fluctuation is provided. A source signal line driver circuit has a plurality of analog buffer circuits, the plurality of source signal lines and the plurality of analog buffer circuits constitute a circuit group, and source signal lines connected to the analog buffer circuits are switched their connections to different analog buffer circuits each time a new period is started. Therefore, output fluctuation among the analog buffer circuits is averaged and a uniform image can be displayed on the screen.

    摘要翻译： 提供一种具有减少亮度波动的模拟缓冲电路的液晶显示装置。 源信号线驱动电路具有多个模拟缓冲电路，多个源极信号线和多个模拟缓冲电路构成电路组，连接到模拟缓冲电路的源极信号线将其连接切换到不同的模拟缓冲器 每次启动一个新的时期的电路。 因此，模拟缓冲电路之间的输出波动被平均化并且可以在屏幕上显示均匀的图像。

    Circuit having source follower and semiconductor device having the circuit
    55.
    发明申请
    Circuit having source follower and semiconductor device having the circuit 失效
    具有源极跟随器和具有该电路的半导体器件的电路

    公开(公告)号：US20050041021A1

    公开(公告)日：2005-02-24

    申请号：US10893936

    申请日：2004-07-20

    申请人： Hiroyuki Miyake ,  Yutaka Shionoiri

    发明人： Hiroyuki Miyake ,  Yutaka Shionoiri

    IPC分类号： G09G3/20 ,  G09G5/00 ,  H03F1/30 ,  H03F3/50 ,  H03K19/00

    CPC分类号： G09G3/20 ,  G09G2310/0275 ,  H03F1/301 ,  H03F3/505

    摘要： When a potential of a power supply line varies according to a flowing current, the gate-source voltage Vgs of a transistor also varies, leading to variations in the constant current between each source follower. In order to solve this problem, a potential Vb of the gate terminal of a transistor as a constant current source is changed in the same manner as a power supply line Vss which is connected to the source terminal of the transistor. Therefore, variations in the constant current are suppressed and variations in the output of the source followers are thus suppressed. In addition, by connecting the circuit having source followers to the output side of a signal line driver circuit, it can be prevented that luminance unevenness of a striped pattern is recognized in a display portion of a semiconductor device.

    摘要翻译： 当电源线的电位根据流动电流而变化时，晶体管的栅极 - 源极电压Vgs也变化，导致每个源极跟随器之间的恒定电流的变化。 为了解决这个问题，作为恒流源的晶体管的栅极端子的电势Vb以与连接到晶体管的源极端子的电源线Vss相同的方式改变。 因此，抑制恒定电流的变化，从而抑制源极跟随器的输出的变化。 此外，通过将具有源极跟随器的电路连接到信号线驱动电路的输出侧，可以防止在半导体器件的显示部分中识别出条纹图案的亮度不均匀。

    Pulse output circuit, shift register and electronic equipment
    56.
    发明授权
    Pulse output circuit, shift register and electronic equipment 有权
    脉冲输出电路，移位寄存器和电子设备

    公开(公告)号：US06813332B2

    公开(公告)日：2004-11-02

    申请号：US10756428

    申请日：2004-01-14

    申请人： Shou Nagao ,  Yoshifumi Tanada ,  Yutaka Shionoiri ,  Hiroyuki Miyake

    发明人： Shou Nagao ,  Yoshifumi Tanada ,  Yutaka Shionoiri ,  Hiroyuki Miyake

    IPC分类号： G11C1900

    CPC分类号： G11C19/28 ,  G09G3/3688 ,  G09G2310/0275 ,  G11C19/00

    摘要： A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node &agr; is raised. When the potential of the node &agr; reaches (VDD−VthN), the node &agr; becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105. An output at the subsequent stage is then inputted to a TFT 103 to turn the TFT 103 On, while the potential of the node &agr; of TFTs 102 and 106 is dropped to turn the TFT 105 OFF. As a result, the potential of the output node becomes Low level.

    摘要翻译： 一种显示装置的驱动电路，其包括单导电类型的TFT并输出具有正常振幅的输出信号。 一个脉冲被输入到TFT101和104，使TFT导通，并且提高节点α的电位。 当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。 因此，随着时钟信号变为高电平，TFT 105导通，输出节点的电位升高。 另一方面，随着输出节点的电位升高，由于电容装置107的操作，TFT 105的栅电极的电位进一步上升，使得TFT 105的栅电极的电位变为 高于（VDD + VthN）。 因此，输出节点的电位升高到VDD，而不会由于TFT105的阈值电压引起电压降。然后，后级的输出被输入到TFT 103，使TFT 103导通，而电位 的TFT102和106的节点α的下降以使TFT 105关闭。 结果，输出节点的电位变为低电平。

    Semiconductor device
    57.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09123581B2

    公开(公告)日：2015-09-01

    申请号：US13287569

    申请日：2011-11-02

    申请人： Toshihiko Saito ,  Yutaka Shionoiri ,  Kiyoshi Kato

    发明人： Toshihiko Saito ,  Yutaka Shionoiri ,  Kiyoshi Kato

    IPC分类号： G06K19/06 ,  H01L27/12 ,  G06K19/07 ,  H01L21/84

    CPC分类号： H01L27/12 ,  G06K19/0701 ,  G06K19/0715 ,  G06K19/0723 ,  H01L21/84

    摘要： An object of the present invention is to provide a semiconductor device which can obtain the high potential necessary for writing data to a memory, using a small circuit area. In the present invention, by using as input voltage of a booster circuit not the conventionally used output VDD of a regulator circuit 104, but rather an output VDD0 of a rectifier circuit portion 103, which is a higher potential than the VDD, the high potential necessary for writing data to a memory can be obtained with a small circuit area.

    摘要翻译： 本发明的目的是提供一种使用小电路区域可以获得将数据写入存储器所需的高电位的半导体器件。 在本发明中，通过使用升压电路的输入电压而不是调节器电路104的常规使用的输出VDD，而是使用比VDD高的电压的整流电路部分103的输出VDD0， 可以以小的电路面积获得将数据写入存储器所必需的。

    Memory and driving method of the same
    59.
    发明授权
    Memory and driving method of the same 有权
    内存和驱动方法相同

    公开(公告)号：US07352604B2

    公开(公告)日：2008-04-01

    申请号：US11607053

    申请日：2006-12-01

    申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

    发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

    IPC分类号： G11C17/00

    CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/12

    摘要： According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.

    摘要翻译： 根据本发明，通过减少元件的数量来减小安装面积并提高产量，并且提供了对外围电路的负担较小的存储器及其驱动方法。 本发明包括一个存储单元，其中存储单元包括位线和字线与插在它们之间的绝缘体交叉的区域中的存储元件，列解码器和包括时钟反相器的选择器。 时钟反相器的输入节点连接到位线，而输出节点连接到数据线。 在形成时钟反相器的串联连接的多个晶体管中，源极或漏极连接到高电位侧VDD上的电源的P型晶体管的栅极和N型晶体管的栅极 源极或漏极连接到低电位侧的电源VSS连接到列解码器。