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公开(公告)号：US20090218625A1
公开(公告)日：2009-09-03
申请号：US12421247
申请日：2009-04-09
IPC分类号： H01L27/092 , H01L27/12
CPC分类号： H01L21/823878 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L27/1207
摘要： A semiconductor process and apparatus includes forming first and second metal gate electrodes (151, 161) over a hybrid substrate (17) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). By forming the first gate electrode (151) over a first SOI substrate (90) formed by depositing (100) silicon and forming the second gate electrode (161) over an epitaxially grown (110) SiGe substrate (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.
摘要翻译： 半导体工艺和装置包括通过在第一高k栅极电介质（121）上形成第一栅极电极（151）并在第二栅极电极（121）上形成第二栅极电极（151）而在混合衬底（17）上形成第一和第二金属栅电极（151,161） 电极（161）在与第一栅极电介质（121）不同的至少第二高k栅极电介质（122）之上。 通过在通过在外延生长（110）SiGe衬底（70）上沉积（100）硅并形成第二栅电极（161）而形成的第一SOI衬底（90）上形成第一栅电极（151），高性能CMOS 获得包括具有改善的空穴迁移率的高k金属PMOS栅电极（161）的器件。
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公开(公告)号：US07544575B2
公开(公告)日：2009-06-09
申请号：US11337036
申请日：2006-01-19
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L29/4925 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor process and apparatus provide a polysilicon structure (10) and source/drain regions (12, 14) formed adjacent thereto in which a dual silicide scheme is used to form first silicide regions in the polysilicon, source and drain regions (30, 32, 34) using a first metal (e.g., cobalt). After forming sidewall spacers (40, 42), a second metal (e.g., nickel) is used to form second silicide regions in the polysilicon, source and drain regions (60, 62, 64) to reduce encroachment by the second silicide in the source/drain (62, 64) and to reduce resistance in the polysilicon structure caused by agglomeration and voiding from the first silicide (30).
摘要翻译： 半导体工艺和设备提供了多晶硅结构（10）和与其相邻形成的源/漏区（12,14），其中双硅化物方案用于在多晶硅，源极和漏极区（30,32）中形成第一硅化物区 ，34）使用第一金属（例如钴）。 在形成侧壁间隔物（40,42）之后，使用第二金属（例如镍）在多晶硅，源极和漏极区域（60,62,64）中形成第二硅化物区域，以减少源极中的第二硅化物的侵入 /漏极（62,64），并且降低由第一硅化物（30）的聚集和排空引起的多晶硅结构中的电阻。
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公开(公告)号：US07524707B2
公开(公告)日：2009-04-28
申请号：US11209869
申请日：2005-08-23
IPC分类号： H01L21/44
CPC分类号： H01L21/823878 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L27/1207
摘要： A semiconductor process and apparatus includes forming first and second metal gate electrodes (151, 161) over a hybrid substrate (17) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). By forming the first gate electrode (151) over a first SOI substrate (90) formed by depositing (100) silicon and forming the second gate electrode (161) over an epitaxially grown (110) SiGe substrate (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.
摘要翻译： 半导体工艺和装置包括通过在第一高k栅极电介质（121）上形成第一栅极电极（151）并在第二栅极电极（121）上形成第二栅极电极（151）而在混合衬底（17）上形成第一和第二金属栅电极（151,161） 电极（161）在与第一栅极电介质（121）不同的至少第二高k栅极电介质（122）之上。 通过在通过在外延生长（110）SiGe衬底（70）上沉积（100）硅并形成第二栅电极（161）而形成的第一SOI衬底（90）上形成第一栅电极（151），高性能CMOS 获得包括具有改善的空穴迁移率的高k金属PMOS栅电极（161）的器件。
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公开(公告)号：US07297586B2
公开(公告)日：2007-11-20
申请号：US11043619
申请日：2005-01-26
IPC分类号： H01L21/8238
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L29/517
摘要： A CMOS device is provided which comprises (a) a substrate (103); (b) a gate dielectric layer (107) disposed on the substrate, the gate dielectric comprising a metal oxide; (c) an NMOS electrode (105) disposed on a first region of said gate dielectric; and (d) a PMOS electrode (115) disposed on a second region of said gate dielectric, the PMOS electrode comprising a conductive metal oxide; wherein the surface of said second region of said gate dielectric comprises a material selected from the group consisting of metal oxynitrides and metal silicon-oxynitrides.
摘要翻译： 提供一种CMOS器件，其包括（a）衬底（103）; （b）设置在所述衬底上的栅极电介质层（107），所述栅极电介质包括金属氧化物; （c）设置在所述栅极电介质的第一区域上的NMOS电极（105）; 和（d）设置在所述栅极电介质的第二区域上的PMOS电极（115），所述PMOS电极包括导电金属氧化物; 其中所述栅极电介质的所述第二区域的表面包括选自金属氧氮化物和金属硅氧氮化物的材料。
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55.发明授权公开(公告)号：US07132360B2
公开(公告)日：2006-11-07
申请号：US10865268
申请日：2004-06-10
IPC分类号： H01L21/4763 , H01L21/8344 , H01L21/8242 , H01L21/336
CPC分类号： H01L21/02181 , C23C16/0272 , H01L21/3141 , H01L21/31645
摘要： A method for treating a semiconductor surface to form a metal-containing layer includes providing a semiconductor substrate having an exposed surface. The exposed surface of the semiconductor substrate is treated by forming one or more metals overlying the semiconductor substrate but not completely covering the exposed surface of the semiconductor substrate. The one or more metals enhance nucleation for subsequent material growth. A metal-containing layer is formed on the exposed surface of the semiconductor substrate that has been treated. The treatment of the exposed surface of the semiconductor substrate assists the metal-containing layer to coalesce. In one embodiment, treatment of the exposed surface to enhance nucleation may be performed by spin-coating, atomic layer deposition (ALD), physical layer deposition (PVD), electroplating, or electroless plating. The one or more metals used to treat the exposed surface may include any rare earth or transition metal, such as, for example, hafnium, lanthanum, etc.
摘要翻译： 一种用于处理半导体表面以形成含金属层的方法包括提供具有暴露表面的半导体衬底。 半导体衬底的暴露表面通过形成覆盖半导体衬底但不完全覆盖半导体衬底的暴露表面的一种或多种金属来处理。 一种或多种金属增强成核以用于随后的材料生长。 在已经处理的半导体衬底的暴露表面上形成含金属层。 半导体衬底的暴露表面的处理有助于含金属层的聚结。 在一个实施方案中，可以通过旋涂，原子层沉积（ALD），物理层沉积（PVD），电镀或无电镀来进行暴露表面的处理以增强成核。 用于处理暴露表面的一种或多种金属可以包括任何稀土或过渡金属，例如铪，镧等。
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公开(公告)号：US06849487B2
公开(公告)日：2005-02-01
申请号：US10445791
申请日：2003-05-27
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L29/51 , H01L29/786
CPC分类号： H01L29/785 , B82Y10/00 , H01L21/28035 , H01L21/28123 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28273 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66795 , Y10S438/947
摘要： A method of forming a conductive structure having a length that is less than the length define by photolithographic patterning. A silicon layer (12) is formed in a MeOx dielectric layer (11) is photolithographically patterned to a predetermined first length. A metal layer (31) is formed conformally to at least the sidewalls of the silicon layer and then is reacted with the silicon to form a metal silicide (41). In particular, metal silicide abutments (411,412) are formed contiguous to sidewalls (421,422) of a reduced conductor (42). The remaining metal layer and the metal silicide are etched away, resulting in a conductor having predetermined second length that is less than the predetermined first length.
摘要翻译： 通过光刻图案形成具有小于长度的长度的导电结构的方法。 在MeOx电介质层（11）中形成的硅层（12）被光刻地图案化到预定的第一长度。 金属层（31）至少与硅层的侧壁共形形成，然后与硅反应形成金属硅化物（41）。 特别地，与还原导体（42）的侧壁（421,422）邻接地形成金属硅化物接合部（411,412）。 蚀刻剩余的金属层和金属硅化物，导致具有小于预定第一长度的预定第二长度的导体。
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公开(公告)号：US06255204B1
公开(公告)日：2001-07-03
申请号：US09316012
申请日：1999-05-21
IPC分类号： H01L214763
CPC分类号： H01L29/66545 , H01L21/28079 , H01L21/28088 , H01L29/495 , H01L29/4966 , H01L29/6656 , H01L29/7842
摘要： A first metal-containing material (22) is formed over a semiconductor device substrate (10). A second metal-containing material (32) is formed over the first metal containing material (22). The combination of the second metal-containing material (32) formed over the first metal-containing material (22) forms a metal stack (34). The metal stack (34) is annealed and a post-anneal stress of the metal stack (34) is less than an individual post-anneal stress of either one of the first conductive film (22) or the second conductive film (32).
摘要翻译： 第一含金属材料（22）形成在半导体器件衬底（10）上。 在第一含金属材料（22）之上形成第二含金属材料（32）。 形成在第一含金属材料（22）上方的第二含金属材料（32）的组合形成金属叠层（34）。 金属叠层（34）退火，并且金属叠层（34）的退火后应力小于第一导电膜（22）或第二导电膜（32）中的任一个的单个后退火应力。
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