公开(公告)号：US08402352B2

公开(公告)日：2013-03-19

申请号：US12704231

申请日：2010-02-11

申请人： Yufei Li ,  Yong Lu ,  Ying Wang ,  Hao Yang

发明人： Yufei Li ,  Yong Lu ,  Ying Wang ,  Hao Yang

IPC分类号： H03M13/00

CPC分类号： H03M13/1575 ,  G06F11/10 ,  G11C2029/0411 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/1565 ,  H03M13/17 ,  H03M13/3746

摘要： Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.

公开(公告)号：US08320169B2

公开(公告)日：2012-11-27

申请号：US13333598

申请日：2011-12-21

申请人： Wenzhong Zhu ,  Yong Lu ,  Xiaobin Wang ,  Yiran Chen ,  Alan Xuguang Wang ,  Xiaohua Lou ,  Haiwen Xi

发明人： Wenzhong Zhu ,  Yong Lu ,  Xiaobin Wang ,  Yiran Chen ,  Alan Xuguang Wang ,  Xiaohua Lou ,  Haiwen Xi

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1675

摘要： An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.

摘要翻译： 一种用于补偿非易失性单元中不对称写入电流的装置和方法。 单位单元包括开关装置和非对称电阻感测元件（RSE），诸如非对称电阻随机存取存储器（RRAM）元件或非对称自旋转矩传递随机存取存储器（STRAM）元件。 RSE相对于开关装置在物理上定位在单位单元内，使得用于编程RSE的硬方向与单元单元的简单编程方向对齐，并且用于编程RSE的简单方向与硬方向对齐 编程单元格

公开(公告)号：US08296620B2

公开(公告)日：2012-10-23

申请号：US12198516

申请日：2008-08-26

申请人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

发明人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

IPC分类号： G06F11/00

CPC分类号： G06F11/1048 ,  G11C2029/0411

摘要： A method of utilizing at least one block of data, wherein the at least one block of data includes a plurality of cells for storing data and at least one error flag bit, the method including: scanning the block of data for errors; determining the error rate of the block of data; and applying an error correction code to data being read from or written to a cell within the at least one block of data, wherein the error correction code is applied based on the error rate, wherein a weak error correction code is applied when the error rate is below an error threshold, and a strong error correction code is applied when the error rate is at or above the error threshold.

摘要翻译： 一种使用至少一个数据块的方法，其中所述至少一个数据块包括用于存储数据的多个单元和至少一个误差标志位，所述方法包括：扫描所述数据块的错误; 确定数据块的错误率; 以及对所述至少一个数据块中的单元读取或写入的数据应用纠错码，其中，基于所述错误率应用所述纠错码，其中当所述错误率 低于错误阈值，并且当错误率处于或高于错误阈值时应用强纠错码。

公开(公告)号：US20120230094A1

公开(公告)日：2012-09-13

申请号：US13476368

申请日：2012-05-21

申请人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

发明人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

IPC分类号： G11C11/16

CPC分类号： G11C7/14 ,  G11C7/02 ,  G11C7/04 ,  G11C7/062 ,  G11C11/1673

摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.

摘要翻译： 存储器阵列包括多个磁阻改变存储单元。 每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。 晶体管在源极区域和漏极区域之间具有电门，并且源极区域电连接在r磁阻变化存储器单元和栅极之间。 字线电耦合到门。 还公开了用于磁阻改变存储器的位线电荷累积感测。

公开(公告)号：US08125819B2

公开(公告)日：2012-02-28

申请号：US13206749

申请日：2011-08-10

申请人： Yong Lu ,  Harry Hongyue Liu

发明人： Yong Lu ,  Harry Hongyue Liu

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/79

摘要： Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.

公开(公告)号：US20120039112A1

公开(公告)日：2012-02-16

申请号：US13280109

申请日：2011-10-24

申请人： Chulmin Jung ,  Yong Lu ,  Insik Jin ,  YoungPil Kim ,  Harry Hongyue Liu

发明人： Chulmin Jung ,  Yong Lu ,  Insik Jin ,  YoungPil Kim ,  Harry Hongyue Liu

IPC分类号： G11C11/00

CPC分类号： A01H6/14 ,  A01H5/02

摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.

摘要翻译： 一种用于从非易失性存储单元读取数据的方法和装置。 在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列。 提供了选择电路，其能够在禁用第二存储单元块的同时激活存储器单元的第一块。 此外，提供一种读取电路，其能够通过对与第一存储器块相对应的块选择元件编程第一电阻状态，以减小的漏电流来读取存储器单元的第一块中的预定存储器单元的逻辑状态 同时将第二电阻状态编程到对应于存储器单元的第二块的块选择元件。

公开(公告)号：US20120039111A1

公开(公告)日：2012-02-16

申请号：US13278334

申请日：2011-10-21

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： G11C11/00 ,  H01L29/78 ,  H01L45/00

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.

摘要翻译： 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻读出存储单元电连接到位触点。 源触点被更多地注入掺杂剂材料，然后进行位接触。

公开(公告)号：US20120037875A1

公开(公告)日：2012-02-16

申请号：US13280392

申请日：2011-10-25

申请人： Roger Glenn Rolbiecki ,  Andrew Carter ,  Yong Lu

发明人： Roger Glenn Rolbiecki ,  Andrew Carter ,  Yong Lu

IPC分类号： H01L45/00

CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/11803 ,  H01L27/228 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233

摘要： A memory comprising at least one memory cell operationally connected to a bit line, a source line and a word line. The memory cell comprises a substrate having a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact, a first transistor gate electrically connecting the first source contact and the bit contact and a second transistor gate electrically connecting the bit contact and the second source contact. The word line electrically connects the first transistor gate to the second transistor gate.

摘要翻译： 一种存储器，包括至少一个可操作地连接到位线，源极线和字线的存储单元。 存储单元包括具有第一源极触点，第二源极触点和第一源极触点和第二源极触点之间的位接触的基板，电连接第一源极触点和位触点的第一晶体管栅极和第二晶体管 栅极电连接位触点和第二源触点。 字线将第一晶体管栅极电连接到第二晶体管栅极。

公开(公告)号：US20110299323A1

公开(公告)日：2011-12-08

申请号：US13206550

申请日：2011-08-10

申请人： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

发明人： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0002 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0069

摘要： A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.

摘要翻译： 一种用于将数据写入诸如RRAM存储器单元的非易失性存储单元的方法和装置。 在一些实施例中，非易失性存储单元的半导体阵列包括电阻感测元件（RSE）和开关器件。 多个存储单元的RSE连接到位线，而多个存储单元的开关器件连接到字线并被操作以选择存储器单元。 源极线连接到开关器件，并将一系列存储器单元连接在一起。 此外，驱动器电路连接到位线，并且通过使写入电流沿着通过所选择的RSE的写入电流路径并通过至少一部分 剩余的RSE连接到所选择的源线。

公开(公告)号：US08072014B2

公开(公告)日：2011-12-06

申请号：US12903301

申请日：2010-10-13

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： G11C11/00 ,  H01L29/78

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.

摘要翻译： 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻读出存储单元电连接到位触点。 源触点被更多地注入掺杂剂材料，然后进行位接触。