公开(公告)号：US20110260233A1

公开(公告)日：2011-10-27

申请号：US12886421

申请日：2010-09-20

申请人： Bich-Yen Nguyen ,  Carlos Mazure ,  Richard Ferrant

发明人： Bich-Yen Nguyen ,  Carlos Mazure ,  Richard Ferrant

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L21/823462 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/0705 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7881

摘要： The present invention relates to a semiconductor device that has a semiconductor-on-insulator (SeOI) structure, which includes a substrate, an insulating layer such as an oxide layer on the substrate and a semiconductor layer on the insulating layer with a field-effect-transistor (FET) formed in the SeOI structure from the substrate and deposited layers, wherein the FET has a channel region in the substrate, a gate dielectric layer that is made from at least a part of the oxide layer of the SeOI structure; and a gate electrode that is formed at least partially from a part of the semiconductor layer of the SeOI structure. The invention further relates to a method of forming one or more field-effect-transistors or metal-oxide-semiconductor transistors from a semiconductor-on-insulator structure that involves patterning and etching the SeOI structure, forming shallow trench isolations, depositing insulating, metal or semiconductor layers, and removing mask and/or pattern layers.

摘要翻译： 本发明涉及一种具有绝缘体上半导体（SeOI）结构的半导体器件，其包括衬底，绝缘层如衬底上的氧化物层和具有场效应的绝缘层上的半导体层 - 晶体管（FET），其从所述衬底和沉积层形成在所述SeOI结构中，其中所述FET在所述衬底中具有沟道区;栅极介电层，其由所述SeOI结构的所述氧化物层的至少一部分制成; 以及至少部分地由SeOI结构的半导体层的一部分形成的栅电极。 本发明还涉及从绝缘体上半导体结构形成一个或多个场效应晶体管或金属氧化物半导体晶体管的方法，该方法包括图案化和蚀刻SeOI结构，形成浅沟槽隔离，沉积绝缘金属 或半导体层，以及去除掩模和/或图案层。

公开(公告)号：US08035163B2

公开(公告)日：2011-10-11

申请号：US12470253

申请日：2009-05-21

申请人： Bich-Yen Nguyen ,  Carlos Mazure

发明人： Bich-Yen Nguyen ,  Carlos Mazure

IPC分类号： H01L29/66 ,  H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76254 ,  H01L21/76256

摘要： In preferred embodiments, the invention provides substrates that include a support, a first insulating layer arranged on the support, a non-mono-crystalline semi-conducting layer arranged on the first insulating layer, a second insulating layer arranged on the non-mono-crystalline semi-conducting layer; and top layer disposed on the second insulating layer. Additionally, a first gate electrode can be formed on the top layer and a second gate electrode can be formed in the non-mono-crystalline semi-conducting layer. The invention also provides methods for manufacture of such substrates.

摘要翻译： 在优选实施例中，本发明提供了包括支撑件，布置在支撑件上的第一绝缘层，布置在第一绝缘层上的非单晶半导体层的衬底，布置在非单晶半导体层上的第二绝缘层， 结晶半导体层; 以及设置在第二绝缘层上的顶层。 此外，可以在顶层上形成第一栅电极，并且可以在非单晶半导体层中形成第二栅电极。 本发明还提供了制造这种基材的方法。

公开(公告)号：US20110233675A1

公开(公告)日：2011-09-29

申请号：US13039167

申请日：2011-03-02

申请人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

发明人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1203

摘要： An SRAM-type memory cell that includes a semiconductor on insulator substrate having a thin film of semiconductor material separated from a base substrate by an insulating layer; and six transistors such as two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters. Each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential. The first and second potentials can be modulated according to the type of cell control operation.

摘要翻译： 一种SRAM型存储单元，包括绝缘体上半导体衬底，其具有通过绝缘层从基底衬底分离的半导体材料薄膜; 以及六个晶体管，例如两个存取晶体管，两个导通晶体管和两个电荷晶体管，其布置成与导通晶体管形成两个反向耦合的反相器。 每个晶体管具有形成在通道下方的基底衬底中的后控制栅极，并且能够被偏置以便调制晶体管的阈值电压，第一背栅极线将存取晶体管的背控制栅极连接到 第一电位和第二背栅极线，其将导通晶体管和电荷晶体管的背控制栅极连接到第二电位。 第一和第二电位可以根据电池控制操作的类型进行调制。

公开(公告)号：US20110037150A1

公开(公告)日：2011-02-17

申请号：US12989474

申请日：2009-05-18

申请人： Bich-Yen Nguyen

发明人： Bich-Yen Nguyen

IPC分类号： H01L29/04 ,  G03F7/20 ,  H01L21/30

CPC分类号： H01L21/76254 ,  H01L21/76256

摘要： A support having a larger density of crystalline defects, an insulating layer disposed on a first region of a front face of the support, and a superficial layer disposed on the insulating layer. An additional layer can be disposed at least on a second region of the front face of the support has a thickness sufficient to bury crystalline defects of the support. A substrate can also include an epitaxial layer arranged at least over the first region of the front face of the support, between the support and the insulation layer. Also, a method of making the substrate by forming a masking layer on the first region of the superficial layer and removing the superficial layer and the insulating layer in the second region uncovered by the masking layer. The additional layer is formed in the second region and then planarized.

摘要翻译： 具有较大结晶缺陷密度的支撑体，设置在支撑体正面的第一区域上的绝缘层和设置在绝缘层上的表面层。 可以至少在支撑体的前表面的第二区域上设置附加层，其厚度足以埋设支撑体的结晶缺陷。 衬底还可以包括布置在支撑体的前表面的至少第一区域之间，在支撑体和绝缘层之间的外延层。 此外，通过在表层的第一区域上形成掩模层并除去由掩模层未覆盖的第二区域中的表层和绝缘层来制造衬底的方法。 附加层形成在第二区域中，然后平坦化。

公开(公告)号：US07838345B2

公开(公告)日：2010-11-23

申请号：US11416436

申请日：2006-05-02

申请人： Zhonghai Shi ,  Bich-Yen Nguyen ,  Héctor Sánchez

发明人： Zhonghai Shi ,  Bich-Yen Nguyen ,  Héctor Sánchez

IPC分类号： H01L21/00

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and contacting each of the first semiconductor fin and the second semiconductor fin along only a portion of length of each of the first semiconductor fin and the second semiconductor fin, respectively. In another aspect, a process for forming an electronic device can include forming a first semiconductor fin and a second semiconductor fin from a semiconductor layer, each of the first semiconductor fin and the second semiconductor fin spaced-apart from the other. The process can also include forming a bridge that contacts the first semiconductor fin and second semiconductor fin. The process can further include forming a conductive member, including a gate electrode, lying between the first semiconductor fin and second semiconductor fin.

摘要翻译： 电子设备可以包括与另一个间隔开的第一半导体鳍片和第二半导体鳍片。 电子设备还可以分别包括位于第一半导体鳍片和第二半导体鳍片之间并且分别仅与第一半导体鳍片和第二半导体鳍片的每一个的长度的一部分接触的桥接器。 在另一方面，一种用于形成电子器件的方法可以包括从半导体层形成第一半导体鳍片和第二半导体鳍片，每个第一半导体鳍片和第二半导体鳍片彼此间隔开。 该工艺还可以包括形成接触第一半导体鳍片和第二半导体鳍片的桥。 该方法还可以包括形成位于第一半导体鳍片和第二半导体鳍片之间的包括栅电极的导电构件。

公开(公告)号：US20100289113A1

公开(公告)日：2010-11-18

申请号：US12726800

申请日：2010-03-18

申请人： Konstantin Bourdelle ,  Bich-Yen Nguyen ,  Mariam Sadaka

发明人： Konstantin Bourdelle ,  Bich-Yen Nguyen ,  Mariam Sadaka

IPC分类号： H01L29/06 ,  H01L21/22

CPC分类号： H01L21/2007 ,  H01L21/187 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/1207

摘要： The present invention relates to a method for manufacturing a hybrid semiconductor substrate comprising the steps of (a) providing a hybrid semiconductor substrate comprising a semiconductor-on-insulator (SeOI) region, that comprises an insulating layer over a base substrate and a SeOI layer over the insulating layer, and a bulk semiconductor region, wherein the SeOI region and the bulk semiconductor region share the same base substrate; (b) providing a mask layer over the SeOI region; and (c) forming a first impurity level by doping the SeOI region and the bulk semiconductor region simultaneously such that the first impurity level in the SeOI region is contained within the mask. Thereby avoiding higher number of process steps involved in the manufacturing process of hybrid semiconductor substrate.

摘要翻译： 本发明涉及一种制造混合半导体衬底的方法，包括以下步骤：（a）提供包括绝缘体上半导体（SeOI）区域的混合半导体衬底，其包括在基底衬底上的绝缘层和SeOI层 在绝缘层和体半导体区域之间，其中SeOI区域和体半导体区域共享相同的基底; （b）在SeOI区域上提供掩模层; 和（c）通过同时掺杂SeOI区域和体半导体区域使得SeOI区域中的第一杂质水平包含在掩模内而形成第一杂质水平。 从而避免了混合半导体衬底的制造过程中涉及的更多数量的工艺步骤。

公开(公告)号：US20100059817A1

公开(公告)日：2010-03-11

申请号：US12205438

申请日：2008-09-05

申请人： DANIEL PHAM ,  Bich-Yen Nguyen

发明人： DANIEL PHAM ,  Bich-Yen Nguyen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/28105 ,  H01L29/42372

摘要： A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.

摘要翻译： 半导体器件包括第一导电类型和第一掺杂浓度的半导体层。 用作第一导电类型的漏极的第一半导体区域具有比半导体层更低的掺杂浓度，并且在半导体层之上。 栅极电介质在第一半导体区域之上。 栅极电介质上的栅极电极在中心部分的相对侧上具有含金属的中心部分和第一和第二硅部分。 用作第二导电类型的沟道的第二半导体区域具有在第一硅部分下面的第一部分和栅极电介质。 用作第一导电类型的源的第三半导体区域与第二半导体区域的第一部分横向相邻。 置换硅的含金属中心部分将源极增加到漏极击穿电压。

公开(公告)号：US20090321873A1

公开(公告)日：2009-12-31

申请号：US12470152

申请日：2009-05-21

申请人： Bich-Yen Nguyen ,  Carlos Mazure

发明人： Bich-Yen Nguyen ,  Carlos Mazure

IPC分类号： H01L27/12 ,  H01L21/20

CPC分类号： H01L21/76251

摘要： In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates.

摘要翻译： 在一个实施例中，本发明提供了被构造成使得在其顶层中制造的器件具有与在标准高电阻率衬底中制造的相同器件相似的性质的衬底。 本发明的基板包括具有标准电阻率的支撑体，布置在支撑基板上的具有高电阻率，优选地大于约1000欧姆 - 厘米的半导体层，设置在高电阻率层上的绝缘层，以及顶层 布置在绝缘层上。 本发明还提供了制造这种基底的方法。

公开(公告)号：US07538002B2

公开(公告)日：2009-05-26

申请号：US11361171

申请日：2006-02-24

申请人： Da Zhang ,  Vance H. Adams ,  Bich-Yen Nguyen ,  Paul A. Grudowski

发明人： Da Zhang ,  Vance H. Adams ,  Bich-Yen Nguyen ,  Paul A. Grudowski

IPC分类号： H01L21/336

CPC分类号： H01L29/7846 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78654

摘要： A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.

摘要翻译： 半导体制造工艺包括在晶体管区域的任一侧上形成隔离结构，形成覆盖晶体管区域的栅极结构，去除源极/漏极区域以形成源极/漏极凹部，去除隔离结构的部分以形成凹入的隔离结构;以及 用诸如外延形成的半导体的源极/漏极应力源填充源/漏极凹部。 源极/漏极凹部的下表面优选比凹入的隔离结构的上表面深大约10至30nm。 填充源极/漏极凹部可以在形成凹入的隔离结构之前或之后。 然后将ILD应激源沉积在晶体管区域上，使得ILD应力源与源极/漏极结构的侧壁相邻，从而将ILD应激源耦合到源极/漏极应力源。 ILD应力器优选为压缩或拉伸氮化硅，并且源极/漏极结构优选为硅锗或硅碳。

公开(公告)号：US07494856B2

公开(公告)日：2009-02-24

申请号：US11393340

申请日：2006-03-30

申请人： Da Zhang ,  Ted R. White ,  Bich-Yen Nguyen

发明人： Da Zhang ,  Ted R. White ,  Bich-Yen Nguyen

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/76254 ,  H01L21/76283 ,  H01L29/66772 ,  H01L29/78684

摘要： A semiconductor fabrication process includes forming an etch stop layer (ESL) overlying a buried oxide (BOX) layer and an active semiconductor layer overlying the ESL. A gate electrode is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors are formed on the ESL where the source/drain stressors strain the transistor channel. Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75° C. may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium. The source/drain stressors may be silicon germanium having a second percentage of germanium for P-type transistors, and they may be silicon carbon for N-type transistors.

摘要翻译： 半导体制造工艺包括形成覆盖掩埋氧化物（BOX）层和覆盖ESL的有源半导体层的蚀刻停止层（ESL）。 形成覆盖有源半导体层的栅电极。 蚀刻有源半导体层的源极/漏极区域以露出ESL。 源极/漏极应力源在ESL上形成，其源极/漏极应力应变应变晶体管沟道。 形成ESL可以包括外延生长厚度为约30nm或更小的硅锗ESL。 优选地，有源半导体层蚀刻速率与ESL蚀刻速率的比率超过10:1。 可以使用加热至约75℃温度的NH 4 OH:H 2溶液进行湿式蚀刻来蚀刻源极/漏极区域。 ESL可以是具有第一百分比的锗的硅锗。 源极/漏极应力源可以是对于P型晶体管具有第二百分比的锗的硅锗，并且它们可以是N型晶体管的硅碳。