公开(公告)号：US10741268B2

公开(公告)日：2020-08-11

申请号：US16235698

申请日：2018-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind Ganesan ,  Jaiganesh Balakrishnan ,  Nagarajan Viswanathan ,  Yeswanth Guntupalli ,  Ajai Paulose ,  Mathews John ,  Jagannathan Venkataraman ,  Neeraj Shrivastava

IPC: G11C29/02 ,  G11C17/14 ,  G11C17/16 ,  G11C17/18

Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

公开(公告)号：US10389373B2

公开(公告)日：2019-08-20

申请号：US16204349

申请日：2018-11-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jagannathan Venkataraman ,  Eeshan Miglani

IPC: H03M1/08 ,  H03K17/16 ,  H03M1/74

Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.

公开(公告)号：US10367479B2

公开(公告)日：2019-07-30

申请号：US15980791

申请日：2018-05-16

Applicant: Texas Instruments Incorporated

Inventor： Rahul Sharma ,  Vajeed Nimran ,  Jagannathan Venkataraman ,  Sandeep Kesrimal Oswal

IPC: H03M3/02 ,  H03M1/12 ,  H03M1/34 ,  G11C27/02 ,  G06F3/044 ,  G06G7/184 ,  H03M1/08 ,  H03H19/00 ,  H03H11/12 ,  G01T1/17 ,  H02J7/34 ,  A61B6/03 ,  A61B6/00

Abstract: The disclosure provides a circuit that includes an integrator that generates an integrated signal in response to a current signal. A comparator is coupled to the integrator and receives the integrated signal and a primary reference voltage signal. The comparator generates a feedback signal. A switched capacitor network is coupled across the integrator. The feedback signal activates the switched capacitor network.

公开(公告)号：US10284187B1

公开(公告)日：2019-05-07

申请号：US15884813

申请日：2018-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prasanth K. ,  Jagannathan Venkataraman ,  Eeshan Miglani

IPC: H03K5/24 ,  H03M1/12 ,  H03M1/46 ,  H03M3/00

Abstract: A comparator includes a differential input pair of transistors, a pair of cross coupled n-channel metal-oxide-semiconductor field-effect (NMOS) transistors, a pair of p-channel metal-oxide semiconductor field-effect (PMOS) transistors, a first inverter, and a second inverter. The differential input pair of transistors includes a first input transistor and a second input transistor. The pair of cross coupled NMOS transistors includes a first NMOS transistor and a second NMOS transistor. The pair of PMOS transistors includes a first PMOS transistor and a second PMOS transistor. The pair of PMOS transistors are coupled to the pair of cross coupled NMOS transistors. The first inverter is coupled in series with the first PMOS transistor. The second inverter is coupled in series with the second PMOS transistor.

公开(公告)号：US20190094340A1

公开(公告)日：2019-03-28

申请号：US16128040

申请日：2018-09-11

Applicant: Texas Instruments Incorporated

Inventor： Jagannathan Venkataraman

IPC: G01S7/484 ,  H03M3/00 ,  G01S17/89 ,  H03M1/06

Abstract: The disclosure provides a circuit. The circuit includes an amplifier and a digital to analog converter (DAC). The amplifier receives a reference voltage at an input node of the amplifier. The DAC is coupled to the amplifier through a refresh switch. The DAC includes one or more current elements. Each current element of the one or more current elements receives a clock. The DAC includes one or more switches corresponding to the one or more current elements. A feedback switch is coupled between the one or more switches and a feedback node of the amplifier. The DAC provides a feedback voltage at the feedback node of the amplifier.

公开(公告)号：US10177775B2

公开(公告)日：2019-01-08

申请号：US15927157

申请日：2018-03-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jagannathan Venkataraman ,  Eeshan Miglani

IPC: H03M1/06 ,  H03M1/08 ,  H03K17/16 ,  H03M1/74

Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.

公开(公告)号：US20180269856A1

公开(公告)日：2018-09-20

申请号：US15980791

申请日：2018-05-16

Applicant: Texas Instruments Incorporated

Inventor： Rahul Sharma ,  Vajeed Nimran ,  Jagannathan Venkataraman ,  Sandeep Kesrimal Oswal

IPC: H03H19/00 ,  H03H11/12 ,  G01T1/17 ,  A61B6/03 ,  A61B6/00 ,  H02J7/34

CPC classification number: H03H19/004 ,  A61B6/032 ,  A61B6/4208 ,  G01T1/17 ,  H02J7/345 ,  H03H11/1291

Abstract: The disclosure provides a circuit that includes an integrator that generates an integrated signal in response to a current signal. A comparator is coupled to the integrator and receives the integrated signal and a primary reference voltage signal. The comparator generates a feedback signal. A switched capacitor network is coupled across the integrator. The feedback signal activates the switched capacitor network.

公开(公告)号：US10078134B2

公开(公告)日：2018-09-18

申请号：US14852104

申请日：2015-09-11

Applicant: Texas Instruments Incorporated

Inventor： Raja Reddy Patukuri ,  Jagannathan Venkataraman ,  Prabu Sankar Thirugnanam

IPC: G01S7/486 ,  G01S17/89 ,  H03M1/00

CPC classification number: G01S7/4865 ,  G01S7/4863 ,  G01S17/89 ,  H03M1/00 ,  H03M1/1245 ,  H03M1/1295 ,  H03M1/164 ,  H03M1/361

Abstract: The disclosure provides a circuit. The circuit includes a first analog to digital converter (ADC) that generates a coarse output in response to a first input and a second input. The first ADC generates the coarse output in a differential phase. A pipeline ADC generates a differential signal in response to the coarse output, the first input and the second input. The pipeline ADC generates the differential signal in a common-mode phase. The first ADC generates a common mode signal in the common-mode phase.

公开(公告)号：US10006950B2

公开(公告)日：2018-06-26

申请号：US14694500

申请日：2015-04-23

Applicant: Texas Instruments Incorporated

Inventor： Anand Hariraj Udupa ,  Jagannathan Venkataraman ,  Hussam Ahmed P ,  Sandeep Kesrimal Oswal

IPC: G01R27/08 ,  A61B5/053

CPC classification number: G01R27/08 ,  A61B5/053

Abstract: The disclosure provides a circuit for impedance measurement. The circuit includes an excitation source that generates an excitation signal. A switched resistor network is coupled to the excitation source, and generates an output signal in response to the excitation signal. A sense circuit is coupled to the switched resistor network, and generates a sense signal in response to the output signal. A comparator is coupled to the sense circuit, and generates a clock signal in response to the sense signal. A mixer is coupled to the sense circuit, and multiplies the sense signal and the clock signal to generate a rectified signal. A low pass filter is coupled to the mixer and filters the rectified signal to generate an averaged signal. A processor is coupled to the low pass filter and measures a body impedance from the averaged signal.

公开(公告)号：US20160128160A1

公开(公告)日：2016-05-05

申请号：US14533763

申请日：2014-11-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bharath Patil ,  Jagannathan Venkataraman

IPC: H05B37/02 ,  H05B33/08

CPC classification number: H05B33/0815 ,  G09G2320/064 ,  H02M3/156 ,  H05B33/0818 ,  H05B33/0845 ,  H05B33/0851 ,  H05B37/02 ,  H05B41/3927 ,  Y02B20/346 ,  Y02B20/347 ,  Y10S362/80

Abstract: In an embodiment, method of controlling an illumination device by an output signal of a DC-DC converter is disclosed. The output signal is controlled by a PWM signal. The method includes receiving a feedback signal corresponding to variation in the output signal with respect to a pre-determined output signal, and determining a target duty cycle of the PWM signal based on the feedback signal. The PWM signal of the target duty cycle is capable of enabling the DC-DC converter to generate the pre-determined output signal. The method includes providing the PWM signal of an effective duty cycle equal to the target duty cycle over N switching pulses of the PWM signal to the DC-DC converter. The method provides the PWM signal by providing M switching pulses of a first PWM signal of a first duty cycle, and N−M switching pulses of a second PWM signal of a second duty cycle.

Abstract translation: 在一个实施例中，公开了通过DC-DC转换器的输出信号控制照明装置的方法。 输出信号由PWM信号控制。 该方法包括接收对应于输出信号相对于预定输出信号的变化的反馈信号，以及基于反馈信号确定PWM信号的目标占空比。 目标占空比的PWM信号能够使DC-DC转换器产生预定的输出信号。 该方法包括将PWM信号的N个开关脉冲的等效于目标占空比的有效占空比提供给DC-DC转换器。 该方法通过提供第一占空比的第一PWM信号的M个开关脉冲和第二占空比的第二PWM信号的N-M个开关脉冲来提供PWM信号。