公开(公告)号：US20200041915A1

公开(公告)日：2020-02-06

申请号：US16525510

申请日：2019-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shinn-Sheng YU ,  Ru-Gun LIU ,  Hsu-Ting HUANG ,  Kenji YAMAZOE ,  Minfeng CHEN ,  Shuo-Yen CHOU ,  Chin-Hsiang LIN

IPC: G03F7/20

Abstract: A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)−2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.

公开(公告)号：US20200006121A1

公开(公告)日：2020-01-02

申请号：US16374150

申请日：2019-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun LIU ,  Chin-Hsiang LIN ,  Chih-Ming LAI ,  Wei-Liang LIN ,  Yung-Sung YEN

IPC: H01L21/768 ,  H01L27/12

Abstract: In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.

公开(公告)号：US20200004135A1

公开(公告)日：2020-01-02

申请号：US16453463

申请日：2019-06-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Ting HUANG ,  Ru-Gun LIU ,  Shinn-Sheng YU

IPC: G03F1/36 ,  G06F17/50

Abstract: A method of making a mask includes computing a transmission cross coefficient (TCC) matrix for an optical system for performing a lithography process, wherein computing includes decomposing the transmission cross coefficient matrix into an ideal transmission cross coefficient (TCC) kernel set for a corresponding ideal optical system and at least one perturbation kernel set with coefficients corresponding to optical defects in the optical system, calibrating a lithography model by iteratively adjusting the lithography model based on a comparison between simulated wafer patterns and measured printed wafer patterns, and providing the calibrated lithography model, which includes an ideal TCC kernel set and the at least two perturbation kernels sets and a resist model, to a mask layout synthesis tool to obtain a synthesized mask layout corresponding to a target mask layout for manufacturing the mask using the synthesized mask layout.

公开(公告)号：US20190165177A1

公开(公告)日：2019-05-30

申请号：US16176072

申请日：2018-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang CHEN ,  Chih-Ming LAI ,  Ching-Wei TSAI ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kuo-Cheng CHING ,  Ru-Gun LIU ,  Wei-Hao WU ,  Yi-Hsiung LIN ,  Chia-Hao CHANG ,  Lei-Chun CHOU

IPC: H01L29/78 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US20190157085A1

公开(公告)日：2019-05-23

申请号：US16149577

申请日：2018-10-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming LAI ,  Shih-Ming CHANG ,  Wei-Liang LIN ,  Chin-Yuan TSENG ,  Ru-Gun LIU

IPC: H01L21/033 ,  H01L21/311

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer has a trench. The method includes forming first spacers over inner walls of the trench. The method includes removing a portion of the first spacers. The method includes forming a filling layer into the trench to cover the first spacers. The filling layer and the first spacers together form a strip structure. The method includes removing the first layer. The method includes forming second spacers over two opposite first sidewalls of the strip structure. The method includes forming third spacers over second sidewalls of the second spacers. The method includes removing the filling layer and the second spacers.

公开(公告)号：US20180164695A1

公开(公告)日：2018-06-14

申请号：US15689244

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ken-Hsien HSIEH ,  Wen-Li CHENG ,  Pai-Wei WANG ,  Ru-Gun LIU ,  Chih-Ming LAI

IPC: G03F7/20 ,  G06F17/50 ,  G03F1/22 ,  G03F1/36

CPC classification number: G03F7/70283 ,  G03F1/22 ,  G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70466 ,  G03F7/705 ,  G06F17/5045 ,  G06F17/5081

Abstract: A multiple patterning decomposition method for IC is provided. Features of layout of IC are decomposed into a plurality of nodes. The nodes are classified to assign a plurality of first and second links between the nodes. First and second pseudo colors are assigned to a pair of nodes of each first link. The second links having a pair of nodes both corresponding to the first or second pseudo color are identified. The nodes of the first links are uncolored. A first real color is assigned to the two uncolored nodes of the identified second links in each of the networks. A second real color is assigned to the uncolored nodes connected to the nodes corresponding to the first real color through the first links. First and second masks are formed according to the nodes corresponding to the first and second real colors, respectively.