公开(公告)号：US20140197538A1

公开(公告)日：2014-07-17

申请号：US14218060

申请日：2014-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

IPC: H01L23/532 ,  H01L23/538

CPC classification number: H01L23/5283 ,  H01L21/31053 ,  H01L21/32139 ,  H01L21/7682 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to an interconnect structure. The metal interconnect structure has a metal body disposed over a semiconductor substrate and a projection extending from the metal body. A barrier layer continuously extends over the projection from a first sidewall of metal body to an opposing second sidewall of the metal body. A layer of dielectric material is disposed over the semiconductor substrate at a position abutting the metal body and the projection.

Abstract translation: 本公开涉及互连结构。 金属互连结构具有设置在半导体衬底上的金属体和从金属体延伸的突起。 阻挡层从金属体的第一侧壁延伸到金属体的相对的第二侧壁的突起上。 电介质材料层设置在与金属体和突起物抵接的位置上的半导体衬底之上。

公开(公告)号：US08728936B1

公开(公告)日：2014-05-20

申请号：US13676260

申请日：2012-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

IPC: H01L21/44

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to a method of manufacturing an interconnect structure in which a sacrificial layer is formed over a semiconductor substrate followed by etching of the sacrificial layer to form a first feature. The metal layer is patterned and etched to form a second feature, followed by deposition of a low-k dielectric material. The method allows for formation of an interconnect structure without encountering the various problems presented by porous low-k dielectric damage.

Abstract translation: 本公开涉及一种制造互连结构的方法，其中牺牲层形成在半导体衬底上，随后蚀刻牺牲层以形成第一特征。 金属层被图案化和蚀刻以形成第二特征，随后沉积低k电介质材料。 该方法允许形成互连结构，而不会遇到由多孔低k电介质损伤所呈现的各种问题。

公开(公告)号：US11854836B2

公开(公告)日：2023-12-26

申请号：US18161701

申请日：2023-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L21/48 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/486 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/14

Abstract: An semiconductor device includes a first dielectric layer, an etch stop layer, an interconnect structure, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The interconnect structure includes a conductive via in the first dielectric layer and the etch stop layer, a conductive line over the conductive via, an intermediate conductive layer over the conductive line, and a conductive pillar over the intermediate conductive layer. The interconnect structure is electrically conductive at least from a top of the conductive pillar to a bottom of the conductive via. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, wherein a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.

公开(公告)号：US11848207B2

公开(公告)日：2023-12-19

申请号：US17189130

申请日：2021-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Chih Wei Lu ,  Chung-Ju Lee

IPC: H01L21/033 ,  H01L21/768

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/76877

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.

公开(公告)号：US11563167B2

公开(公告)日：2023-01-24

申请号：US16510296

申请日：2019-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hao Liao ,  Hsi-Wen Tien ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/02 ,  H01L43/12 ,  G11C11/16 ,  H01L27/22

Abstract: A magnetic memory device includes a bottom electrode, a magnetic tunneling junction disposed over the bottom electrode, and a top electrode disposed over the magnetic tunneling junction, wherein the top electrode includes a first top electrode layer and a second top electrode layer above the first top electrode layer, and wherein the second top electrode layer is thicker than the first top electrode layer.

公开(公告)号：US20220344264A1

公开(公告)日：2022-10-27

申请号：US17236234

申请日：2021-04-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC: H01L23/535 ,  H01L21/768

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.

公开(公告)号：US11482447B2

公开(公告)日：2022-10-25

申请号：US16923424

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Shau-Lin Shue ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.

公开(公告)号：US11362030B2

公开(公告)日：2022-06-14

申请号：US16887475

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Teng Dai ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Hsi-Wen Tien ,  Wei-Hao Liao

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive via is disposed within the first ILD layer. A plurality of conductive wires overlie the first ILD layer. A second ILD layer is disposed laterally between the conductive wires, where the second ILD layer comprises a first material. A sidewall spacer structure is disposed between the second ILD layer and the plurality of conductive wires. The sidewall spacer structure continuously extends along opposing sidewalls of each conductive wire. A top surface of the sidewall spacer structure is vertically above a top surface of the plurality of conductive wires, and the sidewall spacer structure comprises a second material different from the first material.

公开(公告)号：US20210391261A1

公开(公告)日：2021-12-16

申请号：US16898705

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hao Liao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer.

公开(公告)号：US11183422B2

公开(公告)日：2021-11-23

申请号：US17065253

申请日：2020-10-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Hsin-Ping Chen ,  Chih-Wei Lu ,  Chung-Ju Lee

IPC: H01L21/768 ,  H01L23/528

Abstract: A semiconductor structure includes an integrated circuit, a first dielectric layer over the integrated circuit, an etch stop layer over the first dielectric layer, a barrier layer over the etch stop layer, a conductive layer over the barrier layer, and a void region vertically extending through the conductive layer, the barrier layer, and the etch stop layer. The void region has an upper portion, a middle portion below the upper portion, and a lower portion below the middle portion, the middle portion. The middle portion is narrower than the upper portion and the lower portion.