公开(公告)号：US08179714B2

公开(公告)日：2012-05-15

申请号：US12865193

申请日：2009-10-16

Applicant: Takeshi Takagi ,  Shunsaku Muraoka ,  Mitsuteru Iijima ,  Ken Kawai ,  Kazuhiko Shimakawa

Inventor： Takeshi Takagi ,  Shunsaku Muraoka ,  Mitsuteru Iijima ,  Ken Kawai ,  Kazuhiko Shimakawa

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/79

Abstract: Provided is a nonvolatile storage device (200) capable of stably operating without increasing a size of a selection transistor included in each of memory cells. The nonvolatile storage device (200) includes: a semiconductor substrate (301) which has a P-type well (301a) of a first conductivity type; a memory cell array (202) which includes memory cells (M11) or the like each of which includes a variable resistance element (R11) and a transistor (N11) that are formed above the semiconductor substrate (301) and connected in series; and a substrate bias circuit (220) which applies, to the P-type well (301a), a bias voltage in a forward direction with respect to a source and a drain of the transistor (N11), when a voltage pulse for writing is applied to the variable resistance element (R11) included in the selected memory cell (M11) or the like.

Abstract translation: 提供一种能够在不增加包含在每个存储单元中的选择晶体管的尺寸的情况下稳定地工作的非易失性存储装置（200）。 非易失性存储装置（200）包括：具有第一导电型的P型阱（301a）的半导体基板（301） 存储单元阵列（202），其包括存储单元（M11）等，每个存储单元包括形成在半导体衬底（301）上并串联连接的可变电阻元件（R11）和晶体管（N11）; 以及衬底偏置电路（220），当用于写入的电压脉冲为写入电压脉冲时，向P型阱（301a）施加相对于晶体管（N11）的源极和漏极的正向偏置电压 应用于所选择的存储单元（M11）等中包含的可变电阻元件（R11）。

公开(公告)号：US20120104351A1

公开(公告)日：2012-05-03

申请号：US13382321

申请日：2011-06-29

Applicant: Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

Inventor： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

IPC: H01L45/00

CPC classification number: H01L27/2409 ,  G11C13/0007 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1633

Abstract: A stacking structure in which a stacked body (21) including a first conductive layer (13), a semiconductor layer (17), and a second conductive layer (18) and an interlayer insulating film (16) are alternately stacked in parallel to a substrate, a plurality of columnar electrodes (12) arranged so as to penetrated through the stacking structure in a stacking direction, a variable resistance layer (14) which is disposed between the columnar electrode (12) and the first conductive layer (13) and which has a resistance value that reversibly changes according to an application of an electric signal are included. The variable resistance layer (14) is formed by oxidizing part of the first conductive layer (13). The variable resistance layer (14) and an insulating film for electrically separating the semiconductor layer (17) and the second conductive layer (18) from the columnar electrode (12) are simultaneously formed in a single oxidation process.

Abstract translation: 层叠结构，其中包括第一导电层（13），半导体层（17）和第二导电层（18）和层间绝缘膜（16）的层叠体（21）与 基板，多个柱状电极（12），被布置成沿堆叠方向穿过堆叠结构，设置在柱状电极（12）和第一导电层（13）之间的可变电阻层（14）和 其具有根据电信号的应用可逆地改变的电阻值。 可变电阻层（14）通过氧化第一导电层（13）的一部分而形成。 在单次氧化过程中同时形成可变电阻层（14）和用于将半导体层（17）和第二导电层（18）与柱状电极（12）电分离的绝缘膜。

公开(公告)号：US20110299322A1

公开(公告)日：2011-12-08

申请号：US13201890

申请日：2011-02-01

Applicant: Mitsuteru Iijima ,  Takeshi Takagi

Inventor： Mitsuteru Iijima ,  Takeshi Takagi

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/72 ,  G11C2213/79 ,  H01L45/08 ,  H01L45/146

Abstract: A method of programming a variable resistance element includes: performing a writing step by applying a writing voltage pulse having a first polarity to a transition metal oxide comprising two metal oxide layers which are stacked, so as to change a resistance state of the transition metal oxide from high to low, each of the two metal oxide layers having a different degree of oxygen deficiency; and performing an erasing step by applying an erasing voltage pulse having a second polarity to the transition metal oxide so as to change the resistance state of the transition metal oxide from low to high, the second polarity being different from the first polarity, wherein |Vw1|>|Vw2| is satisfied, where Vw1 represents a voltage value of the writing voltage pulse for first to N-th writing steps, and Vw2 represents a voltage value of the writing voltage pulse for (N+1)-th and subsequent writing steps, where N is equal to or more than 1, te1>te2 is satisfied, where te1 represents a pulse width of the erasing voltage pulse for first to M-th erasing steps, and te2 represents a pulse width of the erasing voltage pulse for (M+1)-th and subsequent erasing steps, where M is equal to or more than 1, and the (N+1)-th writing step follows the M-th erasing step.

Abstract translation: 编程可变电阻元件的方法包括：通过将包含第一极性的写入电压脉冲施加到包含堆叠的两个金属氧化物层的过渡金属氧化物来进行写入步骤，以改变过渡金属氧化物的电阻状态 从高到低，两个金属氧化物层中的每一个具有不同程度的氧气缺乏; 以及通过向所述过渡金属氧化物施加具有第二极性的擦除电压脉冲以便将所述过渡金属氧化物的电阻状态从低变为高而进行擦除步骤，所述第二极性与所述第一极性不同，其中| Vw1 |> | Vw2 | 其中Vw1表示第一至第N写入步骤的写入电压脉冲的电压值，Vw2表示第（N + 1）个和后续写入步骤的写入电压脉冲的电压值，其中N是 等于或大于1，则te1> te2被满足，其中te1表示用于第一至第M擦除步骤的擦除电压脉冲的脉冲宽度，te2表示（M + 1）个擦除电压脉冲的脉冲宽度， 其中M等于或大于1，并且第（N + 1）个写入步骤在第M擦除步骤之后。

公开(公告)号：US20110140828A1

公开(公告)日：2011-06-16

申请号：US12967624

申请日：2010-12-14

Applicant: Takumi MIKAWA ,  Takeshi Takagi

Inventor： Takumi MIKAWA ,  Takeshi Takagi

IPC: H01C7/18

CPC classification number: H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/124 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1691

Abstract: A nonvolatile memory element comprising: a first electrode 2; a second electrode 6 formed above the first electrode 2; a variable resistance film 4 formed between the first electrode 2 and the second electrode 6, a resistance value of the variable resistance film 4 being increased or decreased by an electric pulse applied between the first and second electrodes 2, 6; and an interlayer dielectric film 3 provided between the first and second electrodes 2, 6, wherein the interlayer dielectric film 3 is provided with an opening extending from a surface thereof to the first electrode 2; the variable resistance film 4 is formed at an inner wall face of the opening; and an interior region of the opening which is defined by the variable resistance film 4 is filled with an embedded insulating film 5.

Abstract translation: 一种非易失性存储元件，包括：第一电极2; 形成在第一电极2上方的第二电极6; 形成在第一电极2和第二电极6之间的可变电阻膜4，通过施加在第一和第二电极2,6之间的电脉冲，可变电阻膜4的电阻值增加或减小; 以及设置在第一和第二电极2,6之间的层间绝缘膜3，其中层间绝缘膜3设置有从其表面延伸到第一电极2的开口; 可变电阻膜4形成在开口的内壁面上; 并且由可变电阻膜4限定的开口的内部区域填充有嵌入绝缘膜5。

公开(公告)号：US20110075469A1

公开(公告)日：2011-03-31

申请号：US12993706

申请日：2010-03-15

Applicant: Zhiqiang Wei ,  Ryotaro Azuma ,  Takeshi Takagi ,  Mitsuteru Iijima ,  Yoshihiko Kanzawa

Inventor： Zhiqiang Wei ,  Ryotaro Azuma ,  Takeshi Takagi ,  Mitsuteru Iijima ,  Yoshihiko Kanzawa

IPC: G11C11/00

CPC classification number: H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/115 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

Abstract: Each of memory cells (MC) includes one transistor and one resistance variable element. The transistor includes a first main terminal, a second main terminal and a control terminal. The resistance variable element includes a first electrode, a second electrode and a resistance variable layer provided between the first electrode and the second electrode. A first main terminal of one of two adjacent memory cells is connected to a second main terminal of the other memory cell, to form a series path (SP) sequentially connecting main terminals of the plurality of memory cells in series. Each of the memory cells is configured such that the control terminal is a part of a first wire (WL) associated with the memory cell or is connected to the first wire associated with the memory cell, the second electrode is a part of a second wire (SL) associated with the memory cell or is connected to the second wire associated with the memory cell; and the first electrode is a part of a series path (SP) associated with the memory cell or is connected to the series path associated with the memory cell.

Abstract translation: 每个存储单元（MC）包括一个晶体管和一个电阻可变元件。 晶体管包括第一主端子，第二主端子和控制端子。 电阻可变元件包括设置在第一电极和第二电极之间的第一电极，第二电极和电阻变化层。 两个相邻存储单元之一的第一主端子连接到另一个存储单元的第二主端子，以形成串联连接多个存储单元的主端子的串行路径（SP）。 每个存储器单元被配置为使得控制端子是与存储器单元相关联的第一布线（WL）的一部分或者连接到与存储单元相关联的第一布线，第二电极是第二布线 （SL），或者连接到与存储器单元相关联的第二线; 并且第一电极是与存储器单元相关联的或连接到与存储器单元相关联的串联路径的串联路径（SP）的一部分。

公开(公告)号：US07916516B2

公开(公告)日：2011-03-29

申请号：US12524313

申请日：2008-02-22

Applicant: Zhiqiang Wei ,  Kazuhiko Shimakawa ,  Takeshi Takagi ,  Yoshikazu Katoh

Inventor： Zhiqiang Wei ,  Kazuhiko Shimakawa ,  Takeshi Takagi ,  Yoshikazu Katoh

IPC: G11C11/00

CPC classification number: H01L27/101 ,  G11C13/0007 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/1021

Abstract: A nonvolatile memory apparatus comprises a memory array (102) including plural first electrode wires (WL) formed to extend in parallel with each other within a first plane; plural second electrode wires (BL) formed to extend in parallel with each other within a second plane parallel to the first plane and to three-dimensionally cross the plural first electrode wires; and nonvolatile memory elements (11) which are respectively provided at three-dimensional cross points between the first electrode wires and the second electrode wires, the elements each having a resistance variable layer whose resistance value changes reversibly in response to a current pulse supplied between an associated first electrode wire and an associated second electrode wire; and a first selecting device (13) for selecting the first electrode wires, and further comprises voltage restricting means (15) provided within or outside the memory array, the voltage restricting means being connected to the first electrode wires, for restricting a voltage applied to the first electrode wires to a predetermined upper limit value or less; wherein plural nonvolatile memory elements of the nonvolatile memory elements are connected to one first electrode wire connecting the first selecting device to the voltage restricting means.

Abstract translation: 非易失性存储装置包括存储器阵列（102），其包括形成为在第一平面内彼此平行延伸的多个第一电极线（WL） 多个第二电极线（BL），其形成为在与第一平面平行的第二平面内彼此平行延伸并且三维地交叉所述多个第一电极线; 和非易失性存储元件（11），其分别设置在第一电极线和第二电极线之间的三维交叉点处，每个元件具有电阻变化层，其电阻值响应于在 相关联的第一电极线和相关联的第二电极线; 以及用于选择所述第一电极线的第一选择装置（13），并且还包括设置在所述存储器阵列内或外的电压限制装置（15），所述电压限制装置连接到所述第一电极线，用于限制施加到 所述第一电极线达到预定的上限值以下; 其中所述非易失性存储元件的多个非易失性存储元件连接到将所述第一选择装置连接到所述电压限制装置的一个第一电极线。

公开(公告)号：US20110002154A1

公开(公告)日：2011-01-06

申请号：US12677404

申请日：2009-07-01

Applicant: Satoru Mitani ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Takeshi Takagi

Inventor： Satoru Mitani ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Takeshi Takagi

IPC: G11C11/00 ,  H01L45/00 ,  H01L21/16

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/79 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

Abstract: A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (108); a resistance variable layer (107) which is interposed between the first electrode (103) and the second electrode (107) and is configured to switch a resistance value reversibly in response to an electric signal applied between the electrodes (103) and (108), and the resistance variable layer (107) has at least a multi-layer structure in which a first hafnium-containing layer having a composition expressed as HfOx (0.9≦x≦1.6), and a second hafnium-containing layer having a composition expressed as HfOy (1.8

Abstract translation: 本发明的非易失性存储元件包括第一电极（103），第二电极（108） 介于第一电极（103）和第二电极（107）之间的电阻变化层（107），其被配置为响应于施加在电极（103）和（108）之间的电信号可逆地切换电阻值， ，并且电阻变化层（107）具有至少多层结构，其中具有表示为HfO x（0.9＆nlE; x＆nlE; 1.6）的组成的第一含铪层和具有组成的第二含铪层 表示为HfOy（1.8

公开(公告)号：US20100264392A1

公开(公告)日：2010-10-21

申请号：US12742841

申请日：2008-11-14

Applicant: Yoshio Kawashima ,  Takumi Mikawa ,  Ryoko Miyanaga ,  Takeshi Takagi

Inventor： Yoshio Kawashima ,  Takumi Mikawa ,  Ryoko Miyanaga ,  Takeshi Takagi

IPC: H01L45/00 ,  H01L21/02

CPC classification number: H01L27/101 ,  G11C13/0002 ,  G11C2213/72 ,  H01L27/24

Abstract: A nonvolatile memory device includes via holes (12) formed at cross sections where first wires (11) cross second wires (14), respectively, and current control elements (13) each including a current control layer (13b), a first electrode layer (13a) and a second electrode layer (13c) such that the current control layer (13b) is sandwiched between the first electrode layer (13a) and the second electrode layer (13c), in which resistance variable elements (15) are provided inside the via holes (12), respectively, the first electrode layer (13a) is disposed so as to cover the via hole (12), the current control layer (13b) is disposed so as to cover the first electrode layer (13a), the second electrode layer (13c) is disposed on the current control layer (13b), a wire layer (14a) of the second wire is disposed on the second electrode layer (13c), and the second wires (14) each includes the current control layer (13b), the second electrode layer (13c) and the wire layer (14a) of the second wire.

Abstract translation: 非易失性存储器件包括分别形成在第一布线（11）与第二布线（14）交叉的横截面处的通孔（12），以及各自包括电流控制层（13b）的电流控制元件（13），第一电极层 （13a）和第二电极层（13c），使得电流控制层（13b）夹在第一电极层（13a）和第二电极层（13c）之间，其中电阻可变元件（15）设置在其内 通孔（12）分别设置成覆盖通孔（12），电流控制层（13b）被设置成覆盖第一电极层（13a）， 第二电极层（13c）设置在电流控制层（13b）上，第二导线的导线层（14a）设置在第二电极层（13c）上，第二导线（14）各自包括电流 控制层（13b），第二电极层（13c）和第二wi的导线层（14a） 回覆。

公开(公告)号：US20100193760A1

公开(公告)日：2010-08-05

申请号：US12669174

申请日：2008-07-11

Applicant: Takeshi Takagi ,  Takumi Mikawa ,  Koji Arita ,  Mitsuteru Iijima ,  Takashi Okada

Inventor： Takeshi Takagi ,  Takumi Mikawa ,  Koji Arita ,  Mitsuteru Iijima ,  Takashi Okada

IPC: H01L45/00 ,  H01L27/04 ,  H01L21/02

CPC classification number: H01L27/101 ,  H01L27/1021 ,  H01L27/24 ,  H01L45/00

Abstract: In a current rectifying element (10), a barrier height φA of a center region (14) of a barrier layer (11) in a thickness direction thereof sandwiched between a first electrode layer (12) and a second electrode layer (13) is formed to be larger than a barrier height φB of a region in the vicinity of an interface (17) between the barrier layer (11) and the first electrode layer (12) and an interface (17) between the barrier layer (11) and the second electrode layer (13). The barrier layer (11) has, for example, a triple-layer structure of barrier layers (11a), (11b) and (11c). The barrier layers (11a), (11b) and (11c) are, for example, formed by SiN layers of SiNx2, SiNx1, and SiNx1 (X1

Abstract translation: 在电流整流元件（10）中，阻挡层（11）在其厚度方向上的中心区域（14）的阻挡高度＆amp; A被夹在第一电极层（12）和第二电极层（13）之间 ）形成为大于阻挡层（11）和第一电极层（12）之间的界面（17）附近的区域和阻挡层（17）之间的界面（17）的势垒高度B （11）和第二电极层（13）。 阻挡层（11）具有例如阻挡层（11a），（11b）和（11c）的三层结构。 阻挡层（11a），（11b）和（11c）例如由SiNx2，SiNx1和SiNx1（X1

公开(公告)号：US20100090193A1

公开(公告)日：2010-04-15

申请号：US12445380

申请日：2007-10-12

Applicant: Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima ,  Koji Arita

Inventor： Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima ,  Koji Arita

IPC: H01L47/00

CPC classification number: H01L27/101 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1683

Abstract: A lower electrode (22) is provided on a semiconductor chip substrate (26). A lower electrode (22) is covered with a first interlayer insulating layer (27) from above. A first contact hole (28) is provided on the lower electrode (22) to penetrate through the first interlayer insulating layer (27). A low-resistance layer (29) forming the resistance variable layer (24) is embedded to fill the first contact hole (28). A high-resistance layer (30) is provided on the first interlayer insulating layer (27) and the low-resistance layer (29). The resistance variable layer (24) is formed by a multi-layer resistance layer including a single layer of the high-resistance layer (30) and a single layer of the low-resistance layer (29). The low-resistance layer (29) forming the memory portion (25) is isolated from at least its adjacent memory portion (25).

Abstract translation: 下电极（22）设置在半导体芯片基板（26）上。 下部电极（22）从上方被第一层间绝缘层（27）覆盖。 第一接触孔（28）设置在下电极（22）上以穿透第一层间绝缘层（27）。 嵌入形成电阻变化层（24）的低电阻层（29）以填充第一接触孔（28）。 在第一层间绝缘层（27）和低电阻层（29）上设置有高电阻层（30）。 电阻变化层（24）由包含单层高电阻层（30）和单层低电阻层（29）的多层电阻层形成。 形成存储器部分（25）的低电阻层（29）至少与其相邻的存储器部分（25）隔离。