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61 条记录 (耗时 0.037 秒)

    Providing shared and non-shared access to memory in a system with plural processor coherence domains
    52.
    发明授权
    Providing shared and non-shared access to memory in a system with plural processor coherence domains 有权
    在具有多个处理器相干域的系统中提供对存储器的共享和非共享访问

    公开(公告)号：US07069306B1

    公开(公告)日：2006-06-27

    申请号：US09910591

    申请日：2001-07-20

    申请人： Daniel E. Lenoski ,  Jeffrey S. Kuskin ,  William A. Huffman ,  Michael S Woodacre

    发明人： Daniel E. Lenoski ,  Jeffrey S. Kuskin ,  William A. Huffman ,  Michael S Woodacre

    IPC分类号： G06F15/16 ,  G06F12/08

    CPC分类号： G06F12/0817 ,  G06F12/0813

    摘要： A method and system for managing memory in a multiprocessor system includes defining the plurality of processor coherence domains within a system coherence domain of the multiprocessor system. The processor coherence domains each include a plurality of processors and a processor memory. Shared access to data in the processor memory of each processor coherence domain is provided only to elements of the multiprocessor system within the processor coherence domain. Non-shared access to data in the processor memory of each processor coherence domain is provided to elements of the multiprocessor system within and outside of the processor coherence domain.

    摘要翻译： 用于管理多处理器系统中的存储器的方法和系统包括在多处理器系统的系统相干域内定义多个处理器相干域。 处理器相干域各自包括多个处理器和处理器存储器。 每个处理器一致性域的处理器存储器中的数据的共享访问仅提供给处理器相干域内的多处理器系统的元件。 每个处理器相干域的处理器存储器中的数据的非共享访问被提供给处理器相干域内部和外部的多处理器系统的元件。

    System and method for handling updates to memory in a distributed shared memory system
    53.
    发明授权
    System and method for handling updates to memory in a distributed shared memory system 有权
    用于处理分布式共享内存系统中内存更新的系统和方法

    公开(公告)号：US06915387B1

    公开(公告)日：2005-07-05

    申请号：US09910589

    申请日：2001-07-20

    申请人： William A. Huffman ,  Jeffrey S. Kuskin

    发明人： William A. Huffman ,  Jeffrey S. Kuskin

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0822 ,  G06F12/0831

    摘要： A processor (100) in a distributed shared memory computer system (10) receives ownership of data and initiates an initial update to memory request. A front side bus processor interface (24) forwards the initial update to memory request to a memory directory interface unit (22). The front side processor interface (24) may receive subsequent update to memory requests for the data from processors co-located on the same local bus. Front side bus processor interface (24) maintains a most recent subsequent update to memory in a queue (102). Once the data has been updated in its home memory (17), the memory directory interface unit (22) sends a writeback acknowledge to the front side bus processor interface (24). The most recent subsequent update to memory request in the queue (102) is then forwarded by the front side bus processor interface (24) to the memory directory interface unit (24) for processing.

    摘要翻译： 分布式共享存储器计算机系统（10）中的处理器（100）接收数据的所有权并启动对存储器请求的初始更新。 前端总线处理器接口（24）将初始更新转发到存储器请求到存储器目录接口单元（22）。 前侧处理器接口（24）可以接收来自同一位于同一局部总线上的来自处理器的数据的存储器请求的后续更新。 前端总线处理器接口（24）维持对队列（102）中的存储器的最新的后续更新。 一旦在其家庭存储器（17）中更新了数据，存储器目录接口单元（22）向前端总线处理器接口（24）发送回写确认。 然后，队列（102）中对存储器请求的最新的后续更新然后由前端总线处理器接口（24）转发到存储器目录接口单元（24）以进行处理。

    Method and system for managing data at an input/output interface for a multiprocessor system
    54.
    发明授权
    Method and system for managing data at an input/output interface for a multiprocessor system 有权
    用于在多处理器系统的输入/输出接口处管理数据的方法和系统

    公开(公告)号：US06859863B1

    公开(公告)日：2005-02-22

    申请号：US09910631

    申请日：2001-07-20

    申请人： Steven C. Miller ,  Jeffrey S. Kuskin ,  William A. Huffman

    发明人： Steven C. Miller ,  Jeffrey S. Kuskin ,  William A. Huffman

    IPC分类号： G06F12/08 ,  G06F12/14 ,  G06F12/00

    CPC分类号： G06F12/0817 ,  G06F12/1458 ,  G06F2212/621

    摘要： A multiprocessor system and method includes a processing sub-system including a plurality of processors and a processor memory system. A network is operable to couple the processing sub-system to an input/output (I/O) sub-system. The I/O sub-system includes a plurality of I/O interfaces each operable to couple a peripheral device to the multiprocessor system. The I/O interfaces each include a local memory operable to store a copy of data from the processor memory system for use by a corresponding peripheral device and to delete the copy at a first time event. A directory for the processor is operable to identify the data as owned upon providing the copy to the I/O sub-system and to identify the data as unowned at a second time event.

    摘要翻译： 多处理器系统和方法包括包括多个处理器和处理器存储器系统的处理子系统。 网络可操作以将处理子系统耦合到输入/输出（I / O）子系统。 I / O子系统包括多个I / O接口，每个I / O接口可操作以将外围设备耦合到多处理器系统。 I / O接口各自包括本地存储器，其可操作用于存储来自处理器存储器系统的数据副本，以供对应的外围设备使用，并在第一时间事件中删除副本。 用于处理器的目录可操作以将数据提供给I / O子系统并将数据标识为在第二时间事件中未知的数据。

    System and method for reducing memory latency during read requests
    55.
    发明授权
    System and method for reducing memory latency during read requests 有权
    用于在读请求期间减少内存延迟的系统和方法

    公开(公告)号：US06678798B1

    公开(公告)日：2004-01-13

    申请号：US09909701

    申请日：2001-07-20

    申请人： Jeffrey S. Kuskin ,  William A. Huffman

    发明人： Jeffrey S. Kuskin ,  William A. Huffman

    IPC分类号： G06F1200

    CPC分类号： G06F12/0817 ,  G06F2212/1024

    摘要： A processor (500) issues a read request for data. A processor interface (24) initiates a local search for the requested data and also forwards the read request to a memory directory (24) for processing. While the read request is processing, the processor interface (24) can determine if the data is available locally. If so, the data is transferred to the processor (500) for its use. The memory directory (24) processes the read request and generates a read response therefrom. The processor interface (24) receives the read response and determines whether the data was available locally. If so, the read response is discarded. If the data was not available locally, the processor interface (24) provides the read response to the processor (500).

    摘要翻译： 处理器（500）发出对数据的读取请求。 处理器接口（24）发起对所请求的数据的本地搜索，并且还将读取的请求转发到存储器目录（24）以进行处理。 当读取请求正在处理时，处理器接口（24）可以确定数据是否在本地可用。 如果是这样，数据被传送到处理器（500）供其使用。 存储器目录（24）处理读取请求并从其产生读取响应。 处理器接口（24）接收读取响应并确定数据是否在本地可用。 如果是这样，则读取响应被丢弃。 如果数据在本地不可用，则处理器接口（24）向处理器（500）提供读取响应。

    Asymmetric dichroic dye molecules having poly(arylazo) linking groups, a bis-substituted aryl thiazyl end group, and another end group
    58.
    发明授权
    Asymmetric dichroic dye molecules having poly(arylazo) linking groups, a bis-substituted aryl thiazyl end group, and another end group 失效
    具有聚（芳基偶氮）连接基团的不对称二色性染料分子，双取代芳基噻唑基端基和另一个末端基

    公开(公告)号：US4565424A

    公开(公告)日：1986-01-21

    申请号：US337493

    申请日：1982-01-06

    申请人： William A. Huffman ,  James C. Novack

    发明人： William A. Huffman ,  James C. Novack

    IPC分类号： C09B67/22 ,  C09B31/00 ,  C09B31/04 ,  C09B31/14 ,  C09B35/50 ,  C09K19/60 ,  G02F1/137 ,  G02F1/139 ,  G09F9/00 ,  G09F9/35 ,  C09B31/053 ,  C09B31/18 ,  C09B31/28 ,  C09B31/30

    CPC分类号： C09K19/60 ,  C09B31/00 ,  C09B35/50 ,  C09K19/601

    摘要： A dichroic dyestuff having the formulaQ--A--Zwherein:A is a poly(arylazo) linking group wherein the aryl comprises 6 to 10 carbon atoms and has 4,4'-azo linkages;Q is a bis-substituted aryl thiazyl substituent wherein the aryl comprises 6 to 10 carbon atoms;andZ is selected from the group consisting of naphthalene having an alkyl substituted amino in the 4 position, 2,3-dihydro-2,2'-substituted-perimidine and julolidine groups;forms guest-host combinations with nematic liquid crystals. These dichroic dyes have absorption maxima at wavelengths greater than 600 nanometers and transmit less than 50% of incident light having wavelengths between 600 and 700 nanometers. Thus these dyes, when combined with dichroic dyes which have absorption maxima between 400 and 600 nanometers, and nematic liquid crystals, are useful to provide electro-optical displays which change from clear to a neutral black color or vice versa when an electric field is applied to the electro-optical display.

    摘要翻译： 具有式Q-A-Z的二色性染料，其中：A是聚（芳基偶氮）连接基团，其中芳基包含6至10个碳原子并具有4,4'-偶氮键; Q是双取代的芳基噻唑基取代基，其中芳基包含6至10个碳原子; Z选自4位具有烷基取代氨基的萘，2,3-二氢-2,2'-取代 - 脒基和高洛兰定组; 形成与向列液晶的客体 - 主机组合。 这些二色性染料在波长大于600纳米处具有最大吸收，并且透射小于50％的具有600-700纳米波长的入射光。 因此，这些染料当与吸收最大值在400和600纳米之间的二色性染料和向列型液晶组合时，可用于提供电光显示器，其在施加电场时从透明变为中性黑色或反之亦然 到电光显示器。