公开(公告)号：US20080263332A1

公开(公告)日：2008-10-23

申请号：US11884362

申请日：2005-06-22

申请人： Sami Yehia ,  Krisztian Flautner

发明人： Sami Yehia ,  Krisztian Flautner

IPC分类号： G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/30181 ,  G06F9/3877

摘要： A data processing apparatus and method are provided for processing data under control of a program having program instructions including sequences of individual program instructions corresponding to computational subgraphs identified within the program. Each computational subgraph has a number of input operands and produces one or more output operands. The apparatus comprises an operand store for storing the input and output operands, and processing logic for executing individual program instructions from the program. Also provided is configurable accelerator logic which, in response to reaching an execution point within the program corresponding to a sequence of individual program instructions corresponding to a computational subgraph, evaluates one or more output functions associated with the computational subgraph. The evaluation of each output function generates an output operand for storing in the operand store, and each output operand corresponds to an output that would have been generated had the sequence of individual program instructions corresponding to the computational subgraph have been executed by the processing logic. Configuration storage stores a single look-up table (LUT) configuration for each output function, and for each output function to be evaluated, the accelerator logic is configured dependent on the associated single LUT configuration from the configuration storage, such that on receipt of the input operands of the computational subgraph, the accelerator logic will generate the output operand. This technique has been found to provide a particularly efficient accelerator logic for evaluating output functions associated with computational subgraphs.

摘要翻译： 提供了一种数据处理装置和方法，用于在具有程序指令的程序的控制下处理数据，该程序指令包括与程序内识别的计算子图相对应的各个程序指令的序列。 每个计算子图具有多个输入操作数，并产生一个或多个输出操作数。 该装置包括用于存储输入和输出操作数的操作数存储器和用于从程序执行各个程序指令的处理逻辑。 还提供了可配置加速器逻辑，其响应于到达程序内的执行点，对应于与计算子图对应的单独程序指令的序列，来评估与计算子图相关联的一个或多个输出函数。 每个输出函数的评估产生用于存储在操作数存储中的输出操作数，并且每个输出操作数对应于如果已经由处理逻辑执行了与计算子图对应的各个程序指令的序列，则该输出将被产生。 配置存储器存储用于每个输出功能的单个查找表（LUT）配置，并且对于要评估的每个输出功能，加速器逻辑被配置为取决于来自配置存储器的相关联的单个LUT配置，使得在接收到 输入操作数的计算子图，加速器逻辑将产生输出操作数。 已经发现这种技术提供了用于评估与计算子图相关联的输出函数的特别有效的加速器逻辑。

公开(公告)号：US20080141012A1

公开(公告)日：2008-06-12

申请号：US11905160

申请日：2007-09-27

申请人： Sami Yehia ,  Krisztian Flautner ,  Nathan Clark ,  Amir Hormati ,  Scott Mahlke

发明人： Sami Yehia ,  Krisztian Flautner ,  Nathan Clark ,  Amir Hormati ,  Scott Mahlke

IPC分类号： G06F9/318

CPC分类号： G06F9/30054 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30174 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/45516

摘要： A data processing system is provided having a processor and analysing circuitry for identifying a SIMD instruction associated with a first SIMD instruction set and replacing it by a functionally-equivalent scalar representation and marking that functionally-equivalent scalar representation. The marked functionally-equivalent scalar representation is dynamically translated using translation circuitry upon execution of the program to generate one or more corresponding translated instructions corresponding to a instruction set architecture different from the first SIMD architecture corresponding to the identified SIMD instruction.

摘要翻译： 提供了一种数据处理系统，其具有处理器和分析电路，用于识别与第一SIMD指令集相关联的SIMD指令，并通过功能等效的标量表示代替它并标记该功能等效的标量表示。 标记的功能等效标量表示在执行程序时使用转换电路进行动态转换，以生成对应于与所识别的SIMD指令相对应的第一SIMD架构不同的指令集架构的一个或多个相应的转换指令。

公开(公告)号：US07363176B2

公开(公告)日：2008-04-22

申请号：US11294431

申请日：2005-12-06

申请人： Dipesh Ishwerbhai Patel ,  Krisztian Flautner

发明人： Dipesh Ishwerbhai Patel ,  Krisztian Flautner

IPC分类号： G01R31/36

CPC分类号： G06F1/26 ,  G01R31/3004 ,  G01R31/31718 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Voltage-binning of individual integrated circuits is achieved by operating those integrated circuits at a plurality of required clock frequencies and for each of those frequencies determining the minimum supply voltage level which produces a pass result for a series of applied test vectors.

摘要翻译： 通过以多个所需的时钟频率操作那些集成电路，并且为确定最小供电电压的那些频率中的每个频率来实现各个集成电路的电压分级，其产生一系列应用的测试向量的通过结果。

公开(公告)号：US07356817B1

公开(公告)日：2008-04-08

申请号：US09541444

申请日：2000-03-31

申请人： Erik C. Cota-Robles ,  Krisztian Flautner

发明人： Erik C. Cota-Robles ,  Krisztian Flautner

IPC分类号： G06F9/455

CPC分类号： G06F9/4887 ,  G06F9/45537

摘要： A method for scheduling a plurality of virtual machines includes: determining a resource requirement (Xi) for each virtual machine (VM); determining an interrupt period (Yi) for each VM; and scheduling the plurality of VMs based, at least in part, on each respective Xi and Yi.

摘要翻译： 一种用于调度多个虚拟机的方法包括：为每个虚拟机（VM）确定资源需求（X i i i i）; 确定每个VM的中断周期（Y SUB）; 并且至少部分地基于每个相应的X i和Y i i调度多个VM。

公开(公告)号：US07318143B2

公开(公告)日：2008-01-08

申请号：US11044734

申请日：2005-01-28

申请人： Stuart D. Biles ,  Krisztian Flautner ,  Scott Mahlke ,  Nathan Clark

发明人： Stuart D. Biles ,  Krisztian Flautner ,  Scott Mahlke ,  Nathan Clark

IPC分类号： G06F15/80

CPC分类号： G06F9/3885 ,  G06F8/433 ,  G06F8/44 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/30054 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3806 ,  G06F9/3897

摘要： An information processor for executing a program comprising a plurality of separate program instructions is provided. The processor comprises processing logic operable to individually execute said separate program instructions of said program, an operand store operable to store operand values and an accelerator having a plurality of functional units. The accelerator executes a combined operation corresponding to a computational sub-graph of the separate program instructions by configuring individual ones of said plurality of functional units to perform particular processing operations associated with the combined operation. The accelerator executes the combined operation in dependence upon operand mapping data providing a mapping between operands of the combined operation and storage locations within said operand store and in dependence upon separately specified configuration data providing a mapping between the plurality of functional units and the particular processing operations. The configuration data can be re-used for different operand mappings.

摘要翻译： 提供了一种用于执行包括多个独立程序指令的程序的信息处理器。 处理器包括可操作以单独执行所述程序的所述单独程序指令的处理逻辑，可操作以存储操作数值的操作数存储器和具有多个功能单元的加速器。 加速器通过将所述多个功能单元中的各个功能单元配置为执行与组合操作相关联的特定处理操作，执行与单独程序指令的计算子图相对应的组合操作。 加速器根据操作数映射数据执行组合操作，该数据提供组合操作的操作数与所述操作数存储之间的存储位置之间的映射，并且依赖于提供多个功能单元与特定处理操作之间的映射的单独指定的配置数据 。 配置数据可以重新用于不同的操作数映射。

公开(公告)号：US20070288798A1

公开(公告)日：2007-12-13

申请号：US11889759

申请日：2007-08-16

申请人： Krisztian Flautner ,  Todd Austin ,  David Blaauw ,  Trevor Mudge

发明人： Krisztian Flautner ,  Todd Austin ,  David Blaauw ,  Trevor Mudge

IPC分类号： H02H3/05

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/3287 ,  G11C2207/2281 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/171

摘要： An integrated circuit includes a plurality of processing stages each including processing logic 2, a non-delayed latch 4, a delayed latch 8 and a comparator 6. The non-delayed latch 4 captures an output from the processing logic 2 at a non-delayed capture time. At a later delayed capture time, the delayed latch 8 also captures a value from the processing logic 2. The comparator 6 compares these values and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

摘要翻译： 集成电路包括多个处理级，每个处理级包括处理逻辑2，非延迟锁存器4，延迟锁存器8和比较器6。 非延迟锁存器4在非延迟捕获时间捕获来自处理逻辑2的输出。 在稍后的延迟捕获时间，延迟锁存器8也捕获来自处理逻辑2的值。 比较器6比较这些值，如果它们不相等，则表示非延迟值被捕获得太早，应该被延迟值代替。 非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播 在重新启动时钟之前通过后续的处理逻辑。 调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

公开(公告)号：US20070220235A1

公开(公告)日：2007-09-20

申请号：US11375572

申请日：2006-03-15

申请人： Sami Yehia ,  Krisztian Flautner

发明人： Sami Yehia ,  Krisztian Flautner

IPC分类号： G06F9/40

CPC分类号： G06F9/3802 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3879 ,  G06F9/3897

摘要： An integrated circuit 2 includes a configurable accelerator 14. An instruction identifier 22 identifies subgraphs of program instructions which are capable of being performed as combined complex operations by the configurable accelerator 14. The subgraph identifier 22 reorders the sequence of fetched instructions to enable larger subgraphs of program instructions to be formed for acceleration and uses a postpone buffer 24 to store any postponed instructions which have been pushed later in the instruction stream by the reordering action of the subgraph identifier 22.

摘要翻译： 集成电路2包括可配置加速器14。 指令标识符22识别能够由可配置加速器14作为组合复合操作执行的程序指令的子图。 子图标识符22重新排序获取的指令的顺序，以使得能够形成用于加速的程序指令的较大的子图，并且使用推迟缓冲器24来存储在子图识别符的重新排列动作中已被推送到指令流中的任何推迟的指令 22。

公开(公告)号：US07142996B2

公开(公告)日：2006-11-28

申请号：US10912104

申请日：2004-08-06

申请人： Dipesh Ishwerbhai Patel ,  Krisztian Flautner

发明人： Dipesh Ishwerbhai Patel ,  Krisztian Flautner

IPC分类号： G01R31/36 ,  G06F19/00

CPC分类号： G06F1/26 ,  G01R31/3004 ,  G01R31/31718 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Voltage-binning of individual integrated circuits is achieved by operating those integrated circuits at a plurality of required clock frequencies and for each of those frequencies determining the minimum supply voltage level which produces a pass result for a series of applied test vectors.

摘要翻译： 通过以多个所需的时钟频率操作那些集成电路，并且为确定最小供电电压的那些频率中的每个频率来实现各个集成电路的电压分级，其产生一系列应用的测试向量的通过结果。

公开(公告)号：US20060253666A1

公开(公告)日：2006-11-09

申请号：US11353024

申请日：2006-02-14

申请人： Krisztian Flautner ,  David Blaauw ,  Trevor Mudge ,  Nam Kim ,  Steven Martin

发明人： Krisztian Flautner ,  David Blaauw ,  Trevor Mudge ,  Nam Kim ,  Steven Martin

IPC分类号： G06F12/00

CPC分类号： G11C7/20 ,  G06F12/0893 ,  G06F2212/1028 ,  G11C5/14 ,  G11C5/143 ,  G11C5/144 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12 ,  G11C11/417 ,  G11C2207/2227 ,  Y02D10/13

摘要： A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.

公开(公告)号：US20060200699A1

公开(公告)日：2006-09-07

申请号：US11301240

申请日：2005-12-13

申请人： Krisztian Flautner ,  David Bull ,  Todd Austin ,  David Blaauw ,  Trevor Mudge

发明人： Krisztian Flautner ,  David Bull ,  Todd Austin ,  David Blaauw ,  Trevor Mudge

IPC分类号： G06F11/00

CPC分类号： G06F11/24

摘要： An integrated circuit 2 has a specified range of runtime-variable operating parameters. Data processing circuits 4 within the integrated circuit 2 have associated error detection and error repair mechanisms 6. When operating within a narrow typical-case range of runtime-variable operating parameters the data processing circuits 4 operate correctly and substantially without error. When operating outside of this typical-case range but inside the specified range of permitted values for the run-time variable operating parameters, then the error detection and error repair circuit 6 operate to repair the errors which occur.

摘要翻译： 集成电路2具有指定范围的运行时变量运行参数。 集成电路2内的数据处理电路4具有相关联的错误检测和错误修复机制6。 当数据处理电路4在运行时间可变运行参数的窄典型范围内运行时，数据处理电路4运行正确且基本无误。 当在这种典型情况范围之外运行，但在运行时变量运行参数的允许值的指定范围内时，错误检测和错误修复电路6操作以修复发生的错误。