公开(公告)号：US20060253666A1

公开(公告)日：2006-11-09

申请号：US11353024

申请日：2006-02-14

申请人： Krisztian Flautner ,  David Blaauw ,  Trevor Mudge ,  Nam Kim ,  Steven Martin

发明人： Krisztian Flautner ,  David Blaauw ,  Trevor Mudge ,  Nam Kim ,  Steven Martin

IPC分类号： G06F12/00

CPC分类号： G11C7/20 ,  G06F12/0893 ,  G06F2212/1028 ,  G11C5/14 ,  G11C5/143 ,  G11C5/144 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12 ,  G11C11/417 ,  G11C2207/2227 ,  Y02D10/13

摘要： A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.

公开(公告)号：US20050022094A1

公开(公告)日：2005-01-27

申请号：US10896997

申请日：2004-07-23

申请人： Trevor Mudge ,  Todd Austin ,  David Blaauw ,  Krisztian Flautner

发明人： Trevor Mudge ,  Todd Austin ,  David Blaauw ,  Krisztian Flautner

IPC分类号： G06F11/10 ,  G06F11/16 ,  G06F9/30 ,  G06F9/40 ,  G06F15/00 ,  H03M13/00

CPC分类号： G06F11/1695 ,  G06F9/3861 ,  G06F9/3869 ,  G06F11/0721 ,  G06F11/0793 ,  G06F11/104 ,  G06F11/1608 ,  G06F11/167 ,  G06F11/183

摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

摘要翻译： 集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024.非延迟信号捕获元件1016捕获来自 处理逻辑1014处于非延迟捕获时间。 在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。错误检测电路1026和纠错电路1028检测并校正延迟值中的随机误差并提供错误检查的延迟 比较器1024比较错误检查的延迟值和非延迟值，并且如果它们不相等，则这表示非延迟值被太早捕获，并且应该被错误检查的延迟值替换 值。 非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播 在重新启动时钟之前通过后续的处理逻辑。 调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

公开(公告)号：US20060018171A1

公开(公告)日：2006-01-26

申请号：US11150585

申请日：2005-06-13

申请人： Todd Austin ,  David Blaauw ,  Trevor Mudge ,  Dennis Sylvester ,  Krisztian Flautner

发明人： Todd Austin ,  David Blaauw ,  Trevor Mudge ,  Dennis Sylvester ,  Krisztian Flautner

IPC分类号： G11C7/00

CPC分类号： G06F9/3869 ,  G06F9/3861 ,  G06F11/141 ,  G11C7/04 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/22 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2207/2281

摘要： There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism; a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.

公开(公告)号：US20070288798A1

公开(公告)日：2007-12-13

申请号：US11889759

申请日：2007-08-16

申请人： Krisztian Flautner ,  Todd Austin ,  David Blaauw ,  Trevor Mudge

发明人： Krisztian Flautner ,  Todd Austin ,  David Blaauw ,  Trevor Mudge

IPC分类号： H02H3/05

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/3287 ,  G11C2207/2281 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/171

摘要： An integrated circuit includes a plurality of processing stages each including processing logic 2, a non-delayed latch 4, a delayed latch 8 and a comparator 6. The non-delayed latch 4 captures an output from the processing logic 2 at a non-delayed capture time. At a later delayed capture time, the delayed latch 8 also captures a value from the processing logic 2. The comparator 6 compares these values and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

摘要翻译： 集成电路包括多个处理级，每个处理级包括处理逻辑2，非延迟锁存器4，延迟锁存器8和比较器6。 非延迟锁存器4在非延迟捕获时间捕获来自处理逻辑2的输出。 在稍后的延迟捕获时间，延迟锁存器8也捕获来自处理逻辑2的值。 比较器6比较这些值，如果它们不相等，则表示非延迟值被捕获得太早，应该被延迟值代替。 非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播 在重新启动时钟之前通过后续的处理逻辑。 调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

公开(公告)号：US20060200699A1

公开(公告)日：2006-09-07

申请号：US11301240

申请日：2005-12-13

申请人： Krisztian Flautner ,  David Bull ,  Todd Austin ,  David Blaauw ,  Trevor Mudge

发明人： Krisztian Flautner ,  David Bull ,  Todd Austin ,  David Blaauw ,  Trevor Mudge

IPC分类号： G06F11/00

CPC分类号： G06F11/24

摘要： An integrated circuit 2 has a specified range of runtime-variable operating parameters. Data processing circuits 4 within the integrated circuit 2 have associated error detection and error repair mechanisms 6. When operating within a narrow typical-case range of runtime-variable operating parameters the data processing circuits 4 operate correctly and substantially without error. When operating outside of this typical-case range but inside the specified range of permitted values for the run-time variable operating parameters, then the error detection and error repair circuit 6 operate to repair the errors which occur.

摘要翻译： 集成电路2具有指定范围的运行时变量运行参数。 集成电路2内的数据处理电路4具有相关联的错误检测和错误修复机制6。 当数据处理电路4在运行时间可变运行参数的窄典型范围内运行时，数据处理电路4运行正确且基本无误。 当在这种典型情况范围之外运行，但在运行时变量运行参数的允许值的指定范围内时，错误检测和错误修复电路6操作以修复发生的错误。

公开(公告)号：US20120293212A1

公开(公告)日：2012-11-22

申请号：US13472870

申请日：2012-05-16

申请人： Scott Hanson ,  Dennis Sylvester ,  David Blaauw

发明人： Scott Hanson ,  Dennis Sylvester ,  David Blaauw

IPC分类号： G05F1/10

CPC分类号： G11C5/147 ,  G05F1/561 ,  G05F3/242

摘要： An improved reference current generator is provided. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The result is a power efficient, temperature compensated reference current generator.

摘要翻译： 提供改进的参考电流发生器。 电压差发生器产生由相对小的电位分开的两个电压。 两个紧密分离的电压施加在具有较大阻抗值的电阻元件上，导致小且稳定的参考电流。 结果是功率有效的温度补偿参考电流发生器。

公开(公告)号：US20100327842A1

公开(公告)日：2010-12-30

申请号：US12823160

申请日：2010-06-25

申请人： Mingoo Seok ,  Dennis Sylvester ,  David Blaauw ,  Scott Hanson ,  Gregory Chen

发明人： Mingoo Seok ,  Dennis Sylvester ,  David Blaauw ,  Scott Hanson ,  Gregory Chen

IPC分类号： G05F3/16

CPC分类号： G05F3/242

摘要： An improved voltage reference generator is provided. The voltage reference generator comprises: a first transistor having a gate electrode biased to place the first transistor in a weak inversion mode; and a second transistor connected in series with said first transistor and having a gate electrode biased to place the second transistor in a weak inversion mode, where the threshold voltage of the first transistor is smaller than the threshold voltage of the second transistor and the gate electrode of the second transistor is electrically coupled to a drain electrode of the second transistor and the source electrode of the first transistor to form an output for a reference voltage.

摘要翻译： 提供改进的电压基准发生器。 所述电压参考发生器包括：第一晶体管，具有被偏置以将所述第一晶体管置于弱反相模式的栅电极; 以及与所述第一晶体管串联连接的第二晶体管，并且具有被偏置以将所述第二晶体管置于弱反相模式的栅电极，其中所述第一晶体管的阈值电压小于所述第二晶体管和所述栅电极的阈值电压 的第二晶体管的电极电耦合到第二晶体管的漏电极和第一晶体管的源电极，以形成用于参考电压的输出。

公开(公告)号：US09147443B2

公开(公告)日：2015-09-29

申请号：US13472870

申请日：2012-05-16

申请人： Scott Hanson ,  Dennis Sylvester ,  David Blaauw

发明人： Scott Hanson ,  Dennis Sylvester ,  David Blaauw

IPC分类号： H02M11/00 ,  G11C5/14 ,  G05F1/56 ,  G05F3/24

CPC分类号： G11C5/147 ,  G05F1/561 ,  G05F3/242

摘要： An improved reference current generator is provided. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The result is a power efficient, temperature compensated reference current generator.

摘要翻译： 提供改进的参考电流发生器。 电压差发生器产生由相对小的电位分开的两个电压。 两个紧密分离的电压施加在具有较大阻抗值的电阻元件上，导致小且稳定的参考电流。 结果是功率有效的温度补偿参考电流发生器。

公开(公告)号：US08564275B2

公开(公告)日：2013-10-22

申请号：US12823160

申请日：2010-06-25

申请人： Mingoo Seok ,  Dennis Sylvester ,  David Blaauw ,  Scott Hanson ,  Gregory Chen

发明人： Mingoo Seok ,  Dennis Sylvester ,  David Blaauw ,  Scott Hanson ,  Gregory Chen

IPC分类号： G05F3/16

CPC分类号： G05F3/242

摘要： An improved voltage reference generator is provided. The voltage reference generator comprises: a first transistor having a gate electrode biased to place the first transistor in a weak inversion mode; and a second transistor connected in series with said first transistor and having a gate electrode biased to place the second transistor in a weak inversion mode, where the threshold voltage of the first transistor is smaller than the threshold voltage of the second transistor and the gate electrode of the second transistor is electrically coupled to a drain electrode of the second transistor and the source electrode of the first transistor to form an output for a reference voltage.

摘要翻译： 提供改进的电压基准发生器。 所述电压参考发生器包括：第一晶体管，具有被偏置以将所述第一晶体管置于弱反相模式的栅电极; 以及与所述第一晶体管串联连接的第二晶体管，并且具有被偏置以将所述第二晶体管置于弱反相模式的栅电极，其中所述第一晶体管的阈值电压小于所述第二晶体管和所述栅电极的阈值电压 的第二晶体管的电极电耦合到第二晶体管的漏电极和第一晶体管的源电极，以形成用于参考电压的输出。

公开(公告)号：US20070103995A1

公开(公告)日：2007-05-10

申请号：US11267574

申请日：2005-11-07

申请人： David Blaauw ,  David Bull ,  Shidhartha Das

发明人： David Blaauw ,  David Bull ,  Shidhartha Das

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/418 ,  G11C8/08 ,  G11C8/10

摘要： A signal interface for interfacing with an address decoder and a method of address decoding are disclosed. The signal interface comprises: a signal capture element operable to receive an address portion signal associated with a read access to a memory and to provide a first interim address portion signal and a second interim address portion signal, the signal capture element being operable during a pre-charged period to provide a first pre-charged logic level as the first interim address portion signal and the first pre-charged logic level as the second interim address portion signal, the signal capture element being further operable during an evaluate period to output an address portion logic level representative of the address portion signal as the first interim address portion signal and an inverted address portion logic level representative of an inverted address portion signal as the second interim address portion signal; and an inverter circuit operable to receive the first interim address portion signal and the second interim address portion signal from which a first address portion signal and a second address portion signal is respectively derived, the inverter circuit being operable during the pre-charged period to output to an address decoder a second pre-charged logic level as the first address portion signal and the second pre-charged logic level as the second address portion signal, the receipt of the first address portion signal and the second address portion signal at the second pre-charged logic level causing the address decoder to be prevented from causing a data access to the memory from occurring, the inverter circuit having transfer characteristics which cause the first address portion signal and the second address portion signal to be maintained at voltage levels interpreted by the address decoder as being the second pre-charged logic level should the first interim address portion signal or the second interim address portion signal fail to transition to a valid logic level during the evaluate period. By maintaining the address portion signals in this way prevents the address decoder from selecting multiple word lines which ensures no corruption in the state stored in the memory can result due to the inadvertent flow of charge between cells in different rows of the memory even when metastable signals occur during the read access.