公开(公告)号：US06653688B2

公开(公告)日：2003-11-25

申请号：US10116666

申请日：2002-04-03

申请人： Hiroaki Takasu ,  Jun Osanai

发明人： Hiroaki Takasu ,  Jun Osanai

IPC分类号： H01L2362

CPC分类号： H01L28/20 ,  H01L27/016

摘要： A semiconductor device comprises a MOS transistor and a resistor. The resistor has a P-type resistor formed from a P-type semiconductor, an N-type resistor formed from an N-type semiconductor and disposed adjacent the P-type resistor, and an insulating film disposed between the P-type and N-type resistors. The P-type resistor is arranged at the low potential side of the semiconductor device and the N-type resistor is arranged at the high potential side thereof. A portion of the insulating film between the P-type and N-type resistors is made electrically conductive by irradiating the portion with a laser beam to destroy the insulating property thereof to thereby achieve conductivity between the P-type and N-type resistors. A gate electrode of the MOS transistor is formed of a P-type polysilicon thin film having the same high concentration impurity as that of the region where the P-type resistor is in contact with a metal wiring, thereby enhancing the current driving capacity of a driver MOS.

摘要翻译： 半导体器件包括MOS晶体管和电阻器。 电阻器具有由P型半导体形成的P型电阻器，由N型半导体形成并配置在P型电阻器附近的N型电阻器，以及设置在P型和N型半导体器件之间的绝缘膜， 型电阻。 P型电阻器配置在半导体器件的低电位侧，N型电阻器配置在高电位侧。 P型和N型电阻之间的绝缘膜的一部分通过用激光束照射该部分而导电，从而破坏其绝缘性能，从而实现P型和N型电阻之间的导电性。 MOS晶体管的栅电极由与P型电阻器与金属布线接触的区域具有相同的高浓度杂质的P型多晶硅薄膜形成，从而提高了电流驱动能力 驱动器MOS。

公开(公告)号：US06495884B2

公开(公告)日：2002-12-17

申请号：US09767502

申请日：2001-01-23

申请人： Hirofumi Harada ,  Jun Osanai

发明人： Hirofumi Harada ,  Jun Osanai

IPC分类号： H01L2972

CPC分类号： H01L29/7813 ,  H01L29/42368 ,  H01L29/781

摘要： There are provided a vertical MOS transistor in which a high frequency characteristic is improved by reducing a feedback capacitance, and a method of manufacturing the same. When a gate voltage is applied to a gate electrode, a channel is formed in a p− epitaxial growth layer along a trench, and an electron current flows from an n+ drain layer to the p− epitaxial growth layer. In this case, an overlapping area between a gate and the drain layer through a gate oxide film is smaller than prior art, and the capacitance between the gate and the drain layer is smaller than the prior art. Thus, the feedback capacitance becomes small and the high frequency characteristic is improved. Further, since a portion of the gate oxide film at the bottom of the trench is thicker than the portion at the side wall, the distance between the gate and the n+ semiconductor substrate becomes larger than the prior art, and the capacitance formed between the gate and the n+ semiconductor substrate is smaller than the prior art. Thus, the high frequency characteristic is improved as compared with the prior art.

摘要翻译： 提供了通过减少反馈电容来提高高频特性的垂直MOS晶体管及其制造方法。 当栅极电压施加到栅电极时，沿着沟槽在p外延生长层中形成沟道，并且电子电流从n +漏极层流到p-外延生长层。 在这种情况下，通过栅极氧化膜的栅极和漏极层之间的重叠区域比现有技术小，并且栅极和漏极层之间的电容小于现有技术。 因此，反馈电容变小，提高了高频特性。 此外，由于沟槽底部的栅极氧化膜的一部分比侧壁的部分厚，所以栅极与n +半导体衬底之间的距离变得比现有技术大，并且栅极之间形成的电容 并且n +半导体衬底比现有技术小。 因此，与现有技术相比，高频特性得到改善。

公开(公告)号：US06492236B2

公开(公告)日：2002-12-10

申请号：US10096394

申请日：2002-03-12

申请人： Hiroaki Takasu ,  Jun Osanai

发明人： Hiroaki Takasu ,  Jun Osanai

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/7833

摘要： There is provided a manufacturing method for obtaining an MOS transistor which has a homopolar gate structure and a high-melting metallic silicide structure and is suitable even for high speed operation, while at the same time having a structure in which a sufficient withstand voltage can be attained by forming, by a simple method, low concentration drain regions with a long distance. A source and a drain, which have a low concentration, are formed and a thick insulating film and positive resist is formed (applied) on a gate electrode. Then, the positive resist is exposed at an amount of exposure suitable to expose a portion corresponding to a film thickness of the positive resist formed on a flat portion of the thick insulating film as a base and developed. The thick insulating film is etched by an amount substantially corresponding to a film thickness thereof by anisotropic etching using as a mask those portions of the positive resist partially remaining in a step portion. An impurity having a high concentration is simultaneously introduced into the source, the drain, and the gate electrode using a remaining portion of the thick insulating film as a mask. After that, high-melting metallic silicide is formed on exposed portions of the gate electrode and the source and drain regions of the MOS transistor, respectively.

摘要翻译： 提供一种用于获得具有单极栅极结构和高熔点金属硅化物结构并且甚至适用于高速操作的MOS晶体管的制造方法，同时具有足够的耐受电压的结构 通过简单的方法形成具有长距离的低浓度排放区域来实现。 形成低浓度的源极和漏极，并且在栅极上形成（施加）厚的绝缘膜和正性抗蚀剂。 然后，正极抗蚀剂以适于暴露与形成在厚绝缘膜的平坦部分上的正性抗蚀剂的膜厚度相对应的部分作为基底的曝光量被曝光并显影。 通过使用作为掩模的各向异性蚀刻将厚的绝缘膜蚀刻成基本上对应于其膜厚的量，正极抗蚀剂的那些部分部分残留在台阶部分中。 使用厚绝缘膜的剩余部分作为掩模，同时将高浓度的杂质引入源极，漏极和栅电极。 之后，分别在MOS晶体管的栅极电极和源极和漏极区域的露出部分上形成高熔点金属硅化物。

公开(公告)号：US06369409B1

公开(公告)日：2002-04-09

申请号：US08689867

申请日：1996-08-15

申请人： Hiroaki Takasu ,  Jun Osanai ,  Kenji Kitamura

发明人： Hiroaki Takasu ,  Jun Osanai ,  Kenji Kitamura

IPC分类号： F02K900

CPC分类号： H01L28/20 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0802 ,  H01L27/1203

摘要： It is an object to provide a highly precise bleeder resistance circuit having an accurate voltage division ratio and a small temperature coefficient of the resistance value and a highly precise semiconductor device having a small temperature coefficient using such a bleeder resistance circuit, e.g., a semiconductor device such as a voltage detector and a voltage regulator. Such characteristic features that the potential of electric conductors on the thin film resistors and electric conductors under the thin film resistors of a bleeder resistance circuit using thin film resistors is made almost equal to the potential of respective thin film resistors and that, when polysilicon is used in the thin film resistor, the dispersion of the resistance value is controlled and the temperature dependency of the resistance value is made lower by thinning the film thickness of the polysilicon thin film resistor are constituted.

摘要翻译： 本发明的目的是提供具有精确的分压比和较小的电阻值温度系数的高精度放电电阻电路，以及使用这种泄放电阻电路（例如半导体器件）具有较小温度系数的高精度半导体器件 例如电压检测器和电压调节器。 使用薄膜电阻器的泄放电阻电路的薄膜电阻器和薄膜电阻器下方的电导体的电位与各薄膜电阻器的电位几乎相等的特征在于，当使用多晶硅时 在薄膜电阻器中，控制电阻值的分散，并且通过使多晶硅薄膜电阻器的膜厚变薄来降低电阻值的温度依赖性。

公开(公告)号：US06255700B1

公开(公告)日：2001-07-03

申请号：US08783000

申请日：1997-01-14

申请人： Yoshifumi Yoshida ,  Shinichi Yoshida ,  Yutaka Saitoh ,  Jun Osanai

发明人： Yoshifumi Yoshida ,  Shinichi Yoshida ,  Yutaka Saitoh ,  Jun Osanai

IPC分类号： H01L2978

CPC分类号： H01L21/823842 ,  H01L27/0925

摘要： A semiconductor device comprises a depletion-type NMOS transistor having a source region, a drain region connected to a power supply line, and a gate electrode connected to a ground line. An enhancement-type NMOS transistor has a source connected to the ground line, a drain connected in series with the source of the depletion-type MOS transistor between the power supply line and the ground line to define an output terminal, and a gate electrode connected directly to the output terminal.

摘要翻译： 半导体器件包括具有源极区，连接到电源线的漏极区和连接到地线的栅电极的耗尽型NMOS晶体管。 增强型NMOS晶体管具有连接到地线的源极，与电源线和接地线之间的耗尽型MOS晶体管的源极串联的漏极，以限定输出端子，以及连接到栅极电极 直接输出端子。

公开(公告)号：US6140183A

公开(公告)日：2000-10-31

申请号：US217118

申请日：1998-12-21

申请人： Jun Osanai

发明人： Jun Osanai

IPC分类号： H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/06

CPC分类号： H01L29/66681 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/66674 ,  H01L29/66689

摘要： A method of fabricating a semiconductor device an object of which is to form a semiconductor device having a DMOS with high withstanding pressure and high driving capacity and a highly precise polycrystalline silicon resistor. In the method of fabricating a semiconductor device, by patterning a second polycrystalline silicon resistor using anisotropic etching, the size precision is improved. Further, during the patterning, side spacers are formed on gate electrode side walls formed of first polycrystalline silicon at the same time. The body of the DMOS is doped with the gate electrode and the spacers being the mask. A source region is doped with the gate electrode being the mask after the spacers are removed.

摘要翻译： 一种制造半导体器件的方法，其目的是形成具有高耐受压力和高驱动能力的DMOS和高精度多晶硅电阻器的半导体器件。 在制造半导体器件的方法中，通过使用各向异性蚀刻图案化第二多晶硅电阻器，提高了尺寸精度。 此外，在图案化期间，侧间隔物同时形成在由第一多晶硅形成的栅电极侧壁上。 DMOS的主体掺杂有栅电极，间隔物为掩模。 在去除间隔物之后，源区被掺杂有作为掩模的栅电极。

公开(公告)号：US5696400A

公开(公告)日：1997-12-09

申请号：US522733

申请日：1995-09-01

申请人： Shinichi Yoshida ,  Yutaka Saitoh ,  Jun Osanai

发明人： Shinichi Yoshida ,  Yutaka Saitoh ,  Jun Osanai

IPC分类号： H01L29/78 ,  H01L21/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/76

CPC分类号： H01L27/088 ,  H01L29/7835

摘要： A semiconductor integrated circuit device comprises an input terminal for inputting a voltage, an output terminal for outputting a voltage, a MOS driver disposed between the input terminal and the output terminal for adjusting the voltage of the input terminal and transmitting it to the output terminal, and a MOS control circuit for controlling the MOS driver and feeding back voltage information of the output terminal. Each of the MOS driver and the MOS control circuit has a MOS transistor formed on a semiconductor substrate, and each MOS transistor has a source region, a drain region, a channel region disposed between the source region and the drain region, a gate insulating film disposed over the channel region, and a gate electrode disposed over the gate insulating film. The gate insulating films of the MOS transistors have different film thicknesses.

摘要翻译： 半导体集成电路装置包括用于输入电压的输入端子，用于输出电压的输出端子，设置在输入端子和输出端子之间的MOS驱动器，用于调节输入端子的电压并将其发送到输出端子， 以及用于控制MOS驱动器并反馈输出端子的电压信息的MOS控制电路。 MOS驱动器和MOS控制电路中的每一个具有形成在半导体衬底上的MOS晶体管，并且每个MOS晶体管具有源极区域，漏极区域，设置在源极区域和漏极区域之间的沟道区域，栅极绝缘膜 设置在沟道区域上方，以及设置在栅极绝缘膜上方的栅电极。 MOS晶体管的栅极绝缘膜具有不同的膜厚度。

公开(公告)号：US5663589A

公开(公告)日：1997-09-02

申请号：US314140

申请日：1994-09-28

申请人： Yutaka Saitoh ,  Jun Osanai ,  Yoshikazu Kojima ,  Kazutoshi Ishii

发明人： Yutaka Saitoh ,  Jun Osanai ,  Yoshikazu Kojima ,  Kazutoshi Ishii

IPC分类号： H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L29/76 ,  H01L21/04

CPC分类号： H01L27/0814 ,  Y10S257/907 ,  Y10S257/91

摘要： A semiconductor integrated device having a current regulating diode may be substantially reduced in size and improved in performance by forming the current regulating diode of a plurality of MOS transistors each having a gate, a drain region, and a source region formed in a semiconductor substrate, the source regions and the substrate regions being electrically coupled to each other, the drain regions of at least two of the MOS transistors being electrically coupled, and the source regions of each of the MOS transistors being electrically coupled, the coupled drain regions, the coupled source regions, and the coupled gates forming a drain terminal, a source terminal and a gate terminal, respectively. In order to set a desired regulated current, selected coupling lines in the current regulating diode may be cut. This may be accomplished, for example, by measuring a first current which flows in the drain terminal while applying a first voltage to the gate terminal and a second voltage to the drain terminal relative to an electric potential of the source terminal, then measuring a second current which flows in the drain terminal while applying a third voltage to the gate terminal and the second voltage to the drain terminal relative to an electric potential of the source terminal. In order to achieve the desired current characteristic, selected conductive lines between coupled drains or between coupled sources are then cut.

摘要翻译： 具有电流调节二极管的半导体集成器件可以通过形成多个MOS晶体管的电流调节二极管来大大减小尺寸并提高其性能，每个MOS晶体管具有形成在半导体衬底中的栅极，漏极区域和源极区域， 源极区域和衬底区域彼此电耦合，至少两个MOS晶体管的漏极区域电耦合，并且每个MOS晶体管的源极区域电耦合，耦合的漏极区域，耦合的 源极区域和耦合栅极分别形成漏极端子，源极端子和栅极端子。 为了设定期望的调节电流，可以切断电流调节二极管中的选择的耦合线。 这可以例如通过测量在漏极端子中流动的第一电流，同时向栅极端子施加第一电压，并且相对于源极端子的电位向漏极端子施加第二电压，然后测量第二电压 相对于源极端子的电位向漏极端子施加第三电压而向漏极端子施加第三电压而流过漏极端子的电流。 为了实现期望的电流特性，然后切割耦合的漏极之间或耦合的源之间的选定的导线。

公开(公告)号：US07829354B2

公开(公告)日：2010-11-09

申请号：US12069472

申请日：2008-02-11

申请人： Akiko Tsukamoto ,  Jun Osanai

发明人： Akiko Tsukamoto ,  Jun Osanai

IPC分类号： H01L21/66 ,  H01L31/26 ,  H01L21/82 ,  H01L21/326 ,  H01L21/479

CPC分类号： H01L22/20 ,  H01L22/14

摘要： Deviation occurring in a particular region in a plane of a resistor group which constitutes a semiconductor integrated circuit is improved and a quick increase in yield is accomplished. Provided is a fuse trimming method for a semiconductor device in which circuit elements such as transistors and resistors are formed on a semiconductor wafer and which has fuse elements capable of adjusting a resistance value of the resistors by laser trimming, including a resistor correction step of correcting in the particular region of the semiconductor wafer the resistance value of the resistors based on an amount of deviation from a target value of the resistance value of the resistors.

摘要翻译： 在构成半导体集成电路的电阻体的平面中的特定区域中发生的偏差得到改善，并且产率的快速提高。 提供一种用于半导体器件的熔丝修整方法，其中在半导体晶片上形成诸如晶体管和电阻器的电路元件，并且其具有能够通过激光微调来调节电阻器的电阻值的熔丝元件，包括电阻校正步骤，其校正 在半导体晶片的特定区域中，基于与电阻器的电阻值的目标值的偏差量，电阻器的电阻值。

公开(公告)号：US20100059832A1

公开(公告)日：2010-03-11

申请号：US12584638

申请日：2009-09-09

申请人： Hideo Yoshino ,  Hirofumi Harada ,  Jun Osanai

发明人： Hideo Yoshino ,  Hirofumi Harada ,  Jun Osanai

IPC分类号： H01L27/088

CPC分类号： H01L27/0883 ,  G05F3/24

摘要： Provided is a semiconductor device including a depletion type MOS transistor and an enhancement type MOS transistor. In the semiconductor device, in order to provide a reference voltage generating circuit having an enhanced temperature characteristic or analog characteristic without increasing an area of the semiconductor device through addition of a circuit, well regions of the depletion type MOS transistor and the enhancement type MOS transistor, which have different concentrations from each other, are formed.

摘要翻译： 提供了包括耗尽型MOS晶体管和增强型MOS晶体管的半导体器件。 在半导体器件中，为了提供具有增强的温度特性或模拟特性的参考电压产生电路，而不通过添加电路而增加半导体器件的面积，耗尽型MOS晶体管和增强型MOS晶体管的阱区 形成彼此不同的浓度。