公开(公告)号：US5741717A

公开(公告)日：1998-04-21

申请号：US391283

申请日：1995-02-21

申请人： Tetsuya Nakai ,  Hiroshi Shinyashiki ,  Yasuo Yamaguchi ,  Tadashi Nishimura

发明人： Tetsuya Nakai ,  Hiroshi Shinyashiki ,  Yasuo Yamaguchi ,  Tadashi Nishimura

IPC分类号： H01L21/20 ,  H01L21/02 ,  H01L21/265 ,  H01L21/322 ,  H01L21/324 ,  H01L21/76 ,  H01L21/762 ,  H01L27/00 ,  H01L27/12

CPC分类号： H01L21/324 ,  H01L21/26533 ,  H01L21/76243

摘要： Oxygen ion is implanted into a silicon substrate to remain a silicon layer on a surface of the silicon substrate. In this state, a silicon oxide layer is formed under the silicon layer. Silicon oxide particles are formed and remained in the residual silicon layer. While maintaining this state, the silicon substrate is heated to a predetermined temperature not less than 1300.degree. C. Alternatively, the silicon substrate is heated at a high temperature-rise rate to 900.degree.-1100.degree. C., and thereafter is heated at a low temperature-rise rate to the temperature not less than 1300.degree. C. The silicon substrate is held at the predetermined temperature not less than 1300.degree. C. for a predetermined time, whereby crystallinity of the residual silicon layer is restored. A pinning effect of the silicon oxide particles prevents the rise of dislocation to the surface of the SOI layer, and also suppresses a rate per a unit time at which interstitial silicon generates during the heating to the high temperature region. Therefore, a dislocation density of the SOI layer can be reduced.

摘要翻译： 将氧离子注入硅衬底中以在硅衬底的表面上保留硅层。 在该状态下，在硅层的下方形成氧化硅层。 形成氧化硅颗粒并残留在残余硅层中。 在保持该状态的同时，将硅衬底加热到​​不低于1300℃的预定温度。或者，将硅衬底以高升温速率加热到900-111℃，然后在 低温升温速率不低于1300℃。硅衬底在预定温度不低于1300℃保持预定时间，从而恢复残余硅层的结晶度。 氧化硅颗粒的钉扎效应防止了位于SOI层表面的位错上升，并且还抑制了在加热到高温区域期间间隙硅产生的每单位时间的速率。 因此，可以降低SOI层的位错密度。

公开(公告)号：US5616507A

公开(公告)日：1997-04-01

申请号：US444590

申请日：1995-05-19

申请人： Tetsuya Nakai ,  Yasuo Yamaguchi ,  Tadashi Nishimura

发明人： Tetsuya Nakai ,  Yasuo Yamaguchi ,  Tadashi Nishimura

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/322 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/3226 ,  H01L21/2022 ,  H01L21/26533 ,  H01L21/76243

摘要： A polysilicon layer is formed on a surface of a silicon substrate after oxygen ions are implanted into the silicon substrate and an SiO.sub.2 film is formed in the silicon substrate at a position in a prescribed depth from the surface of silicon substrate. A heat treatment is performed to a silicon layer between the polysilicon layer and the SiO.sub.2 film, thereby providing an SOI layer with improved crystal quality.

摘要翻译： 在将氧离子注入到硅衬底中之后，在硅衬底的表面上形成多晶硅层，并且在硅衬底中形成从硅衬底表面规定深度的位置形成SiO 2膜。 对多晶硅层和SiO 2膜之间的硅层进行热处理，从而提供具有改善的晶体质量的SOI层。

公开(公告)号：US5557231A

公开(公告)日：1996-09-17

申请号：US291057

申请日：1994-08-15

申请人： Yasuo Yamaguchi ,  Tadashi Nishimura

发明人： Yasuo Yamaguchi ,  Tadashi Nishimura

IPC分类号： G11C5/14 ,  G11C11/4074 ,  H01L27/02 ,  H01L27/105 ,  H03K19/00 ,  H01L27/04

CPC分类号： H03K19/0016 ,  G11C11/4074 ,  G11C5/146 ,  H01L27/0218 ,  H01L27/105

摘要： A semiconductor device including an NMOS transistor includes a first bias generating circuit 30 for generating a substrate bias VBB1 for making smaller the amount of leak current in an inactive state, a second bias generating circuit 31 for generating a substrate bias VBB2 for increasing drivability of supplying current in the active state of the NMOS transistor, and a bias selecting circuit 32 responsive to a control signal CNT for supplying the substrate bias VBB2 instead of the substrate bias VBB1 to the silicon substrate 1. By changing the potential of the substrate bias in the standby state and the active state, power consumption in the standby state can be reduced and the speed of operation in the active state can be improved.

摘要翻译： 包括NMOS晶体管的半导体器件包括：第一偏置产生电路30，用于产生用于使无效状态下的漏电流量更小的衬底偏置VBB1;产生用于提高供电的驱动能力的衬底偏置VBB2的第二偏压产生电路31; 电流处于NMOS晶体管的激活状态;以及偏置选择电路32，其响应用于将衬底偏置VBB2而不是衬底偏压VBB1提供给硅衬底1的控制信号CNT。通过改变衬底偏压的电位， 待机状态和活动状态，可以降低备用状态下的功耗，并且可以提高活动状态下的运行速度。

公开(公告)号：US5441899A

公开(公告)日：1995-08-15

申请号：US017257

申请日：1993-02-12

申请人： Tetsuya Nakai ,  Yasuo Yamaguchi ,  Tadashi Nishimura

发明人： Tetsuya Nakai ,  Yasuo Yamaguchi ,  Tadashi Nishimura

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/322 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/3226 ,  H01L21/2022 ,  H01L21/26533 ,  H01L21/76243

摘要： A polysilicon or amorphous Si layer is formed on a surface of a silicon substrate. Oxygen ions are implanted into the silicon substrate through the polysilicon layer, and an SiO.sub.2 film is formed in the silicon substrate at a position in a prescribed depth from the surface of silicon substrate. A heat treatment is performed to a silicon layer between the polysilicon layer and the SiO.sub.2 film, thereby providing an SOI layer with improved crystal quality.

摘要翻译： 在硅衬底的表面上形成多晶硅或非晶Si层。 氧离子通过多晶硅层注入到硅衬底中，并且在硅衬底中在与硅衬底表面规定深度的位置处形成SiO 2膜。 对多晶硅层和SiO 2膜之间的硅层进行热处理，从而提供具有改善的晶体质量的SOI层。

公开(公告)号：US5125007A

公开(公告)日：1992-06-23

申请号：US439680

申请日：1989-11-22

申请人： Yasuo Yamaguchi ,  Tadashi Nishimura

发明人： Yasuo Yamaguchi ,  Tadashi Nishimura

IPC分类号： H01L21/84 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L29/786 ,  H01L29/78612 ,  H01L29/78615 ,  H01L2924/0002

摘要： An MOS field effect transistor comprises a channel region (6) of a first conductivity type formed in a semiconductor layer (3) on an insulator substrate (2), a source region (8) and a drain region (9) of a second conductivity type formed in contact with one and the other sides of the channel region (6) in the semiconductor layer (3), respectively, a body region (7) formed in contact with at least a part of the channel region (6) and a part of a periphery of the source region (8) in the semiconductor layer (3) and having a higher impurity concentration than that of the channel region (6), a gate electric thin film (4) and a gate electrode (5) formed on the channel region (6), and a conductor (14a) connected in common to the source region (8) and the body region (7).

公开(公告)号：US5424225A

公开(公告)日：1995-06-13

申请号：US269287

申请日：1994-06-30

申请人： Yasuo Yamaguchi ,  Tadashi Nishimura

发明人： Yasuo Yamaguchi ,  Tadashi Nishimura

IPC分类号： H01L21/84 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786 ,  H01L21/265 ,  H01L21/266

CPC分类号： H01L29/66772 ,  H01L29/786 ,  H01L29/78612 ,  H01L29/78615 ,  H01L2924/0002

摘要： An MOS field effect transistor comprises a channel region (6) of a first conductivity type formed in a semiconductor layer (3) on an insulator substrate (2), a source region (8) and a drain region (9) of a second conductivity type formed in contact with one and the other sides of the channel region (6) in the semiconductor layer (3), respectively, a body region (7) formed in contact with at least a part of the channel region (6) and a part of a periphery of the source region (8) in the semiconductor layer (3) and having a higher impurity concentration than that of the channel region (6), a gate dielectric thin film (4) and a gate electrode (5) formed on the channel region (6), and a conductor (14a) connected in common to the source region (8) and the body region (7).

摘要翻译： MOS场效应晶体管包括形成在绝缘体基板（2）上的半导体层（3）中的第一导电类型的沟道区（6），具有第二导电性的源区（8）和漏区（9） 分别与半导体层（3）中的沟道区（6）的一侧和另一侧接触形成与沟道区（6）的至少一部分形成的主体区（7）和 半导体层（3）中的源极区域（8）的周边的一部分并且具有比沟道区域（6）的杂质浓度更高的杂质浓度，形成栅极电介质薄膜（4）和栅电极（5） 在沟道区域（6）上，以及与源区（8）和体区（7）共同连接的导体（14a）。

公开(公告)号：US5641980A

公开(公告)日：1997-06-24

申请号：US557558

申请日：1995-11-14

申请人： Yasuo Yamaguchi ,  Hans-Oliver Joachim ,  Yasuo Inoue

发明人： Yasuo Yamaguchi ,  Hans-Oliver Joachim ,  Yasuo Inoue

IPC分类号： H01L29/40 ,  H01L21/336 ,  H01L27/12 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66757 ,  H01L27/1203 ,  H01L29/78606 ,  H01L29/78609 ,  H01L29/78621

摘要： It is an object to obtain a semiconductor device with the LDD structure having both operational stability and high speed and a manufacturing method thereof. A high concentration region (11) with boron of about 1.times.10.sup.18 /cm.sup.3 introduced therein is formed extending from under a channel formation region (4) to under a drain region (6) and a source region (6') in a silicon substrate (1). The high concentration region (11) is formed in the surface of the silicon substrate (1) under the channel formation region (4), and is formed at a predetermined depth from the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). A low concentration region (10) is formed in the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). The formation of the high concentration region only in the surface of the semiconductor substrate under the channel formation region surely suppresses an increase in the leakage current and an increase in the drain capacitance.

摘要翻译： 本发明的目的是获得具有操作稳定性和高速度的LDD结构的半导体器件及其制造方法。 导入其中引入了约1×10 18 / cm 3的硼的高浓度区域（11）形成在沟道形成区域（4）下方延伸到漏极区域（6）下方的硅衬底（1）中的源极区域（6'） ）。 在硅衬底（1）的沟道形成区域（4）的表面上形成高浓度区域（11），并且形成在与硅衬底（1）的漏极区域 6）和源极区（6'）。 在漏极区域（6）和源极区域（6'）的下方的硅衬底（1）的表面中形成低浓度区域（10）。 仅在沟道形成区域的半导体衬底的表面形成高浓度区域确实地抑制了漏电流的增加和漏极电容的增加。

公开(公告)号：US4982102A

公开(公告)日：1991-01-01

申请号：US424924

申请日：1989-10-23

申请人： Yasuo Inoue ,  Yasuo Yamaguchi

发明人： Yasuo Inoue ,  Yasuo Yamaguchi

IPC分类号： G01B11/24 ,  G01B11/25

CPC分类号： G01B11/25

摘要： Disclosed is an apparatus for detecting the three-dimensional configuration of an object employing an optical cutting method. A light projector pulse-flashes slit-shaped light and causes the light to scan an object at a predetermined speed. An image sensor having a plurality of pixels is disposed in opposition to the object. An optical system forms on the image sensor an image of an optical cutting line formed on the surface of the object by the light. Counters each count the number of pulses of the image of the optical cutting line that has been detected by each pixel. A time calculator calculates the time at which the image has passed each of the pixels, on the basis of the counted numbers of pulses. A configuration calculator calculates the three-dimensional configuration of the object on the basis of the calculated passage time and the scanning speed of the slit-shaped light. Because the counted numbers of pulses, which are each indicative of the period of time required for the image of the optical cutting line to pass each pixel, are used to calculate the passage time, there is no need to provide a data bus to transmit time data with respect to the each pixel. Thus, the apparatus has simple wiring arrangement, and can be manufactured with ease.

摘要翻译： 公开了一种使用光学切割方法检测物体的三维构造的装置。 光投射器脉冲闪烁狭缝状光，并使光以预定速度扫描物体。 具有多个像素的图像传感器设置成与物体相对。 光学系统在图像传感器上形成通过光形成在物体表面上的光学切割线的图像。 计数器各自计数由每个像素检测的光学切割线的图像的脉冲数。 时间计算器基于计数的脉冲数来计算图像已经通过每个像素的时间。 配置计算器基于所计算的通过时间和狭缝状光的扫描速度来计算物体的三维配置。 由于计数通过时间的光学切割线的图像所需的时间周期的脉冲的计数数据用于计算通过时间，因此不需要提供数据总线来传送时间 相对于每个像素的数据。 因此，该装置具有简单的布线布置，并且可以容易地制造。

公开(公告)号：US06310377B1

公开(公告)日：2001-10-30

申请号：US09134896

申请日：1998-08-17

申请人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Il Jung Kim ,  Yasuo Inoue ,  Shigeto Maegawa ,  Takashi Ipposhi

发明人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Il Jung Kim ,  Yasuo Inoue ,  Shigeto Maegawa ,  Takashi Ipposhi

IPC分类号： H01L2701

CPC分类号： H01L21/76202 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76291 ,  H01L27/11807 ,  H01L27/1203

摘要： FS-isolated fields (10a, 10b). LOCOS-isolated fields (11c, 11d). FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can he provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.

摘要翻译： FS隔离场（10a，10b）。 LOCOS隔离场（11c，11d）。 FS隔离场（10e，10f），LOCOS隔离场（11g，11h）和FS隔离场（10i）按此顺序排列。 因此，可以提供主布局，其中将具有被提供固定电位的主体和具有不具有固定电位的主体的SOI晶体管混合。

公开(公告)号：US5926703A

公开(公告)日：1999-07-20

申请号：US785277

申请日：1997-01-21

申请人： Yasuo Yamaguchi ,  Hans-Oliver Joachim ,  Yasuo Inoue

发明人： Yasuo Yamaguchi ,  Hans-Oliver Joachim ,  Yasuo Inoue

IPC分类号： H01L29/40 ,  H01L21/336 ,  H01L27/12 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786 ,  H01L21/44

CPC分类号： H01L29/66757 ,  H01L27/1203 ,  H01L29/78606 ,  H01L29/78609 ,  H01L29/78621

摘要： It is an object to obtain a semiconductor device with the LDD structure having both operational stability and high speed and a manufacturing method thereof. A high concentration region (11) with boron of about 1.times.10.sup.18 /cm.sup.3 introduced therein is formed extending from under a channel formation region (4) to under a drain region (6) and a source region (6') in a silicon substrate (1). The high concentration region (11) is formed in the surface of the silicon substrate (1) under the channel formation region (4), and is formed at a predetermined depth from the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). A low concentration region (10) is formed in the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). The formation of the high concentration region only in the surface of the semiconductor substrate under the channel formation region surely suppresses an increase in the leakage current and an increase in the drain capacitance.

摘要翻译： 本发明的目的是获得具有操作稳定性和高速度的LDD结构的半导体器件及其制造方法。 导入其中引入了约1×10 18 / cm 3的硼的高浓度区域（11）形成在沟道形成区域（4）下方延伸到漏极区域（6）下方的硅衬底（1）中的源极区域（6'） ）。 在硅衬底（1）的沟道形成区域（4）的表面上形成高浓度区域（11），并且形成在与硅衬底（1）的漏极区域 6）和源极区（6'）。 在漏极区域（6）和源极区域（6'）的下方的硅衬底（1）的表面中形成低浓度区域（10）。 仅在沟道形成区域的半导体衬底的表面形成高浓度区域确实地抑制了漏电流的增加和漏极电容的增加。