公开(公告)号：US08227899B2

公开(公告)日：2012-07-24

申请号：US12553586

申请日：2009-09-03

申请人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

发明人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L21/71 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.

摘要翻译： 提供了一种装置，其包括位于具有第一和第二相对主表面的基板的第一区域中的集成电路和位于基板的第二区域中并在第一和第二表面之间延伸穿过基板的对准标记。

公开(公告)号：US20090189233A1

公开(公告)日：2009-07-30

申请号：US12020149

申请日：2008-01-25

申请人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Chi-Hsin Lo ,  Feng-Jia Shiu ,  Chung-Yi Yu

发明人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Chi-Hsin Lo ,  Feng-Jia Shiu ,  Chung-Yi Yu

IPC分类号： H01L31/0232 ,  H01L31/18

CPC分类号： H01L27/14625 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14685

摘要： An optical image sensor is fabricated by forming a pixel array and a peripheral region surrounding the pixel array on a semiconductor substrate, the peripheral region containing peripheral circuitry. An inter-level-dielectric layer is formed over the substrate and a plurality of interconnect wiring layers are formed over the inter-level-dielectric layer. Each interconnect wiring layer includes interconnecting metal features and a layer of inter-level-dielectric material covering the interconnecting metal features. The plurality of interconnect wiring layers are provided in a manner that there are N levels of wiring layers in the peripheral region and 1 to (N−1) levels of wiring layers over the pixel array. An etch-stop layer is formed over the top-most level interconnecting metal features in the peripheral region.

摘要翻译： 通过在半导体衬底上形成围绕像素阵列的像素阵列和外围区域来制造光学图像传感器，该外围区域包含外围电路。 层间电介质层形成在衬底之上，并且在层间电介质层之上形成多个互连布线层。 每个互连布线层包括互连金属特征和覆盖互连金属特征的层间电介质材料层。 多个互连布线层的设置方式是在像素阵列的周边区域中有N层布线层和布线层的1层（N-1）层。 在外围区域中最顶层的互连金属特征上形成蚀刻停止层。

公开(公告)号：US08278152B2

公开(公告)日：2012-10-02

申请号：US12626296

申请日：2009-11-25

申请人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Shou-Gwo Wuu

发明人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Shou-Gwo Wuu

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/12 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

摘要： The present disclosure provides a method of making an integrated circuit (IC). The method includes forming an electric device on a front side of a substrate; forming a top metal pad on the front side of the substrate, the top metal pad being coupled to the electric device; forming a passivation layer on the front side of the substrate, the top metal pad being embedded in the passivation layer; forming an opening in the passivation layer, exposing the top metal pad; forming a deep trench in the substrate; filling a conductive material in the deep trench and the opening, resulting in a though-wafer via (TWV) feature in the deep trench and a pad-TWV feature in the opening, where the top metal pad being connected to the TWV feature through the pad-TWV feature; and applying a polishing process to remove excessive conductive material, forming a substantially planar surface.

摘要翻译： 本公开提供了制造集成电路（IC）的方法。 该方法包括在基板的正面上形成电子装置; 在所述基板的前侧形成顶部金属焊盘，所述顶部金属焊盘联接到所述电气装置; 在所述基板的正面上形成钝化层，所述顶部金属焊盘嵌入所述钝化层中; 在钝化层中形成开口，暴露顶部金属垫; 在衬底中形成深沟槽; 在深沟槽和开口中填充导电材料，导致深沟槽中的贯穿晶片通孔（TWV）特征和开口中的焊盘TWV特征，其中顶部金属焊盘通过该沟槽连接到TWV特征 pad-TWV功能; 以及施加抛光工艺以去除过量的导电材料，形成基本平坦的表面。

公开(公告)号：US07994032B2

公开(公告)日：2011-08-09

申请号：US12845496

申请日：2010-07-28

申请人： Shang-Yi Chiang ,  Chung Wang ,  Shou-Gwo Wuu ,  Dun-Nian Yaung

发明人： Shang-Yi Chiang ,  Chung Wang ,  Shou-Gwo Wuu ,  Dun-Nian Yaung

IPC分类号： H01L21/38

CPC分类号： H01L27/14623 ,  H01L27/14627 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/148

摘要： The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a substrate having a front surface and a back surface; a plurality of sensor elements formed on the front surface of the substrate, each of the plurality of sensor elements configured to receive light directed towards the back surface; and an aluminum doped feature formed in the substrate and disposed horizontally between two adjacent elements of the plurality of sensor elements and vertically between the back surface and the plurality of sensor elements.

摘要翻译： 本公开提供了一种图像传感器半导体器件。 半导体器件包括具有前表面和后表面的衬底; 形成在所述基板的前表面上的多个传感器元件，所述多个传感器元件中的每一个被配置为接收朝向所述后表面的光; 以及形成在所述基板中并且水平放置在所述多个传感器元件的两个相邻元件之间并且垂直地位于所述背表面和所述多个传感器元件之间的铝掺杂特征。

公开(公告)号：US07791170B2

公开(公告)日：2010-09-07

申请号：US11456291

申请日：2006-07-10

申请人： Shang-Yi Chiang ,  Chung Wang ,  Shou-Gwo Wuu ,  Dun-Nian Yaung

发明人： Shang-Yi Chiang ,  Chung Wang ,  Shou-Gwo Wuu ,  Dun-Nian Yaung

IPC分类号： H01L25/065

CPC分类号： H01L27/14623 ,  H01L27/14627 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/148

摘要： The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a substrate having a front surface and a back surface; a plurality of sensor elements formed on the front surface of the substrate, each of the plurality of sensor elements configured to receive light directed towards the back surface; and an aluminum doped feature formed in the substrate and disposed horizontally between two adjacent elements of the plurality of sensor elements and vertically between the back surface and the plurality of sensor elements.

摘要翻译： 本公开提供了一种图像传感器半导体器件。 半导体器件包括具有前表面和后表面的衬底; 形成在所述基板的前表面上的多个传感器元件，所述多个传感器元件中的每一个被配置为接收朝向所述后表面的光; 以及形成在所述基板中并且水平放置在所述多个传感器元件的两个相邻元件之间并且垂直地位于所述背表面和所述多个传感器元件之间的铝掺杂特征。

公开(公告)号：US20090146325A1

公开(公告)日：2009-06-11

申请号：US11951916

申请日：2007-12-06

申请人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

发明人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

IPC分类号： H01L23/544 ,  H01L21/46

CPC分类号： H01L23/544 ,  H01L21/71 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An apparatus and manufacturing method thereof, wherein an integrated circuit is located in a first region of a substrate having first and second opposing major surfaces, and wherein an alignment mark is located in a second region of the substrate and extends through the substrate between the first and second surfaces. The alignment mark may protrude from the first and/or second surfaces, and/or may comprise a plurality of substantially similar alignment marks. The second region may interpose the first region and a perimeter of the substrate. The second region may comprise a scribe region.

摘要翻译： 一种装置及其制造方法，其中集成电路位于具有第一和第二相对主表面的基板的第一区域中，并且其中对准标记位于所述基板的第二区域中，并且延伸穿过所述基板在所述第一 和第二表面。 对准标记可以从第一和/或第二表面突出，和/或可以包括多个基本相似的对准标记。 第二区域可以插入衬底的第一区域和周边。 第二区域可以包括划线区域。

公开(公告)号：US6165880A

公开(公告)日：2000-12-26

申请号：US94869

申请日：1998-06-15

申请人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Li-Chih Chao ,  Kuo Ching Huang

发明人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Li-Chih Chao ,  Kuo Ching Huang

IPC分类号： H01L21/285 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/28525 ,  H01L21/32053

摘要： A method was achieved for making improved self-aligned contacts (SAC) to a patterned polysilicon layer, such as gate electrodes for FETs. Lightly doped source/drain areas are implanted. A second insulating layer is deposited and etched back to form first sidewall spacers. A silicon nitride etch-stop layer and a first interpolysilicon oxide (IPO1) layer are deposited. First SAC openings are etched in the IPO1 layer to the etch-stop layer, and concurrently openings are etched for the gate electrodes, eliminating a masking step. The etch-stop layer is etched in the SAC openings to form second sidewall spacers that protect the first sidewall spacers during BOE cleaning of the contacts. A patterned polycide layer is used to make SACs and electrical interconnections. A second IPO layer is deposited to provide insulation, and an interlevel dielectric layer is deposited. Second SAC openings are etched to the etch-stop layer for the next level of metal interconnections, while the contact openings to the gate electrodes are etched to completion. The etch-stop layer is etched in the second SAC openings to form second sidewall spacers to protect the first sidewall spacers during cleaning. Metal plugs are formed from a first metal in the second SAC openings and in the openings to the gate electrodes. A second metal is patterned to complete the structure to the first level of metal interconnections.

摘要翻译： 实现了对图案化多晶硅层（例如FET的栅电极）进行改进的自对准接触（SAC）的方法。 植入轻掺杂的源极/漏极区域。 沉积第二绝缘层并回蚀刻以形成第一侧壁间隔物。 沉积氮化硅蚀刻停止层和第一多晶硅化硅（IPO1）层。 在IPO1层中蚀刻第一SAC开口到蚀刻停止层，同时蚀刻用于栅电极的开口，从而消除掩模步骤。 在SAC开口中蚀刻蚀刻停止层以形成第二侧壁间隔物，其在接触的BOE清洁期间保护第一侧壁间隔物。 使用图案化的多晶硅化合物层来制造SAC和电互连。 沉积第二个IPO层以提供绝缘，并且沉积层间电介质层。 将第二SAC开口蚀刻到蚀刻停止层以进行下一级金属互连，同时蚀刻到栅电极的接触开口以完成。 在第二SAC开口中蚀刻蚀刻停止层以形成第二侧壁间隔物，以在清洁期间保护第一侧壁间隔物。 金属插塞由第二SAC开口中的第一金属和与栅电极的开口形成。 图案化第二金属以将结构完成到第一级金属互连。

公开(公告)号：US5926697A

公开(公告)日：1999-07-20

申请号：US947793

申请日：1997-10-09

申请人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Hsien Wei Chin

发明人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Hsien Wei Chin

IPC分类号： H01L21/02 ,  H01L21/761 ,  H01L23/525 ,  H01L21/76

CPC分类号： H01L28/87 ,  H01L21/761 ,  H01L23/5258 ,  H01L2924/0002

摘要： An improved and new structure and method for forming a guard ring in an integrated circuit having at least one level of polysilicon wiring has been developed. The guard ring is formed without necessitating additional manufacturing process steps and the guard ring is bonded to the semiconductor substrate, thereby providing a superior barrier to diffusion of moisture and contaminants from a window in the insulating layers to the semiconductor device regions.

摘要翻译： 已经开发了用于在具有至少一个级别的多晶硅布线的集成电路中形成保护环的改进和新的结构和方法。 保护环形成，而不需要额外的制造工艺步骤，并且保护环结合到半导体衬底，从而为水分和污染物从绝缘层中的窗口扩散到半导体器件区域提供了优越的屏障。

公开(公告)号：US08383440B2

公开(公告)日：2013-02-26

申请号：US13081120

申请日：2011-04-06

申请人： Wen-De Wang ,  Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Chung-Yi Yu

发明人： Wen-De Wang ,  Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Chung-Yi Yu

IPC分类号： H01L21/00

CPC分类号： H01L27/14654 ,  H01L27/14623 ,  H01L27/14636 ,  H01L2924/0002 ,  H01L2924/00

摘要： System and method for providing a light shield for a CMOS imager is provided. The light shield comprises a structure formed above a point between a photo-sensitive element and adjacent circuitry. The structure is formed of a light-blocking material, such as a metal, metal alloy, metal compound, or the like, formed in dielectric layers over the photo-sensitive elements.

摘要翻译： 提供了一种用于为CMOS成像器提供遮光罩的系统和方法。 光屏蔽包括形成在感光元件和相邻电路之间的点之上的结构。 该结构由光敏元件上的电介质层中形成的诸如金属，金属合金，金属化合物等的遮光材料形成。

公开(公告)号：US20090321888A1

公开(公告)日：2009-12-31

申请号：US12553586

申请日：2009-09-03

申请人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

发明人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L21/71 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.

摘要翻译： 提供了一种装置，其包括位于具有第一和第二相对主表面的基板的第一区域中的集成电路和位于基板的第二区域中并在第一和第二表面之间延伸穿过基板的对准标记。