公开(公告)号：US12249649B2

公开(公告)日：2025-03-11

申请号：US17207751

申请日：2021-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Han Wu ,  Hsin-Yu Chen ,  Chun-Hao Lin ,  Shou-Wei Hsieh ,  Chih-Ming Su ,  Yi-Ren Chen ,  Yuan-Ting Chuang

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/417

Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

公开(公告)号：US12125900B2

公开(公告)日：2024-10-22

申请号：US17983417

申请日：2022-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L29/66 ,  H01L21/762

CPC classification number: H01L29/66628 ,  H01L21/76232 ,  H01L29/6656 ,  H01L29/66787

Abstract: A semiconductor device includes a gate structure on a substrate, a single diffusion break (SDB) structure adjacent to the gate structure, a first spacer adjacent to the gate structure, a second spacer adjacent to the SDB structure, a source/drain region between the first spacer and the second spacer, an interlayer dielectric (ILD) layer around the gate structure and the SDB structure, and a contact plug in the ILD layer and on the source/drain region. Preferably, a top surface of the second spacer is lower than a top surface of the first spacer.

公开(公告)号：US12100750B2

公开(公告)日：2024-09-24

申请号：US18093330

申请日：2023-01-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L29/66 ,  H01L21/762

CPC classification number: H01L29/66628 ,  H01L21/76232 ,  H01L29/6656 ,  H01L29/66787

Abstract: A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.

公开(公告)号：US10991824B2

公开(公告)日：2021-04-27

申请号：US16252715

申请日：2019-01-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Han Wu ,  Hsin-Yu Chen ,  Chun-Hao Lin ,  Shou-Wei Hsieh ,  Chih-Ming Su ,  Yi-Ren Chen ,  Yuan-Ting Chuang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/417

Abstract: A semiconductor device includes: a fin-shaped structure on the substrate; a shallow trench isolation (STI) around the fin-shaped structure; a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure; a second gate structure on the STI; and a third gate structure on the SDB structure, wherein a width of the third gate structure is greater than a width of the second gate structure.

公开(公告)号：US10483395B2

公开(公告)日：2019-11-19

申请号：US15849599

申请日：2017-12-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/027 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first buffer layer on the first fin-shaped structure and the second fin-shaped structure; removing the first buffer layer on the first region; and performing a curing process so that a width of the first fin-shaped structure is different from a width of the second fin-shaped structure.

公开(公告)号：US10446448B2

公开(公告)日：2019-10-15

申请号：US16175776

申请日：2018-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Chun-Tsen Lu ,  Shou-Wei Hsieh

IPC: H01L29/06 ,  H01L21/8234

Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; a first oxide layer on the first fin-shaped structure; a second oxide layer on and directly contacting the first oxide layer and the STI; and a third oxide layer on the second fin-shaped structure, wherein a thickness of the third oxide layer is less than a thickness of the first oxide layer.

公开(公告)号：US10431652B2

公开(公告)日：2019-10-01

申请号：US15834082

申请日：2017-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L29/10 ,  H01L29/775 ,  B82Y10/00 ,  H01L21/324

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.

公开(公告)号：US10340272B2

公开(公告)日：2019-07-02

申请号：US15947862

申请日：2018-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Shou-Wei Hsieh ,  Hsin-Yu Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/51 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088

Abstract: A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a semiconductor substrate. The barrier layer formed in the first region is thinned before a step of forming a first work function layer on the barrier layer. The first work function layer formed on the first region is then removed. The process of thinning the barrier layer in the first region and the process of removing the first work function layer in the first region are performed separately for ensuring the coverage of the first work function layer in the second region. The electrical performance of the semiconductor device and the uniformity of the electrical performance of the semiconductor device may be improved accordingly.

公开(公告)号：US20190189525A1

公开(公告)日：2019-06-20

申请号：US16280043

申请日：2019-02-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/161 ,  H01L27/092

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first gate structure on the first region and a second gate structure on the second region; forming a first spacer around the first gate structure; forming a first epitaxial layer adjacent to two sides of the first spacer; forming a buffer layer on the first gate structure; and forming a contact etch stop layer (CESL) on the buffer layer on the first region and the second gate structure on the second region.

公开(公告)号：US20190131453A1

公开(公告)日：2019-05-02

申请号：US15821860

申请日：2017-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Chun-Jung Tang ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/762

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/167 ,  H01L29/42356 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7848 ,  H01L29/7851

Abstract: A tunnel field effect transistor (TFET) includes: a first gate structure on a substrate; a source region having a first conductive type on one side of the first gate structure; a drain region having a second conductive type on another side of the first gate structure; a first isolation structure adjacent to the source region; and a second isolation structure adjacent to the drain region. Preferably, the first isolation and the second isolation comprise different material and different depths or same material and different depths.