公开(公告)号：US12119272B2

公开(公告)日：2024-10-15

申请号：US18233331

申请日：2023-08-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Chi-Mao Hsu ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Chun-Hsien Lin

IPC: H01L21/00 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823821 ,  H01L27/0924

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.

公开(公告)号：US12046639B2

公开(公告)日：2024-07-23

申请号：US17683288

申请日：2022-02-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Yu-Chi Wang ,  Yen-Hsing Chen ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/15 ,  H01L29/778

CPC classification number: H01L29/151 ,  H01L29/7786

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

公开(公告)号：US11876122B2

公开(公告)日：2024-01-16

申请号：US17994375

申请日：2022-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wei Chang ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Fu-Jung Chuang ,  Shao-Wei Wang ,  Yu-Ren Wang ,  Chia-Yuan Chang

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/08 ,  H01L29/24 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/4983 ,  H01L21/0234 ,  H01L21/02332 ,  H01L21/02521 ,  H01L21/28123 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a semiconductor device. A substrate having a fin structure is provided. A dummy gate is formed on the fin structure. A polymer block is formed adjacent to a corner between the dummy gate and the fin structure. The polymer block is subjected to a nitrogen plasma treatment, thereby forming a nitridation layer in proximity to a sidewall of the dummy gate under the polymer block. After subjecting the polymer block to the nitrogen plasma treatment, a seal layer is formed on the sidewall of the dummy gate and on the polymer block. An epitaxial layer is then grown on a source/drain region of the fin structure. The dummy gate is then replaced with a metal gate.

公开(公告)号：US11791413B2

公开(公告)日：2023-10-17

申请号：US17392222

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Shih-Cheng Chen ,  Chia-Wei Chang ,  Chia-Ming Kuo ,  Tsai-Yu Wen ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L23/10

CPC classification number: H01L29/7851 ,  H01L21/02126 ,  H01L23/10 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66795

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.

公开(公告)号：US20230253457A1

公开(公告)日：2023-08-10

申请号：US18135203

申请日：2023-04-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Yu-Chi Wang ,  Yen-Hsing Chen ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/15 ,  H01L29/778

CPC classification number: H01L29/151 ,  H01L29/7786

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

公开(公告)号：US20230014253A1

公开(公告)日：2023-01-19

申请号：US17392222

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Shih-Cheng Chen ,  Chia-Wei Chang ,  Chia-Ming Kuo ,  Tsai-Yu Wen ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L23/10

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.

公开(公告)号：US11527448B2

公开(公告)日：2022-12-13

申请号：US17134465

申请日：2020-12-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Chi-Mao Hsu ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Chun-Hsien Lin

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.

公开(公告)号：US20220208694A1

公开(公告)日：2022-06-30

申请号：US17179422

申请日：2021-02-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Hsing Chen ,  Yu-Ming Hsu ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L23/00 ,  H01L29/20

Abstract: A semiconductor structure includes a substrate including a device region, a peripheral region surrounding the device region, and a transition region disposed between the device region and the peripheral region. An epitaxial layer is disposed on the device region, the peripheral region, and the transition region. A first portion of the epitaxial layer on the peripheral region has a poly-crystal structure.

公开(公告)号：US20210249528A1

公开(公告)日：2021-08-12

申请号：US16843851

申请日：2020-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Yen-Hsing Chen ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/778 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.

公开(公告)号：US20210151591A1

公开(公告)日：2021-05-20

申请号：US16711451

申请日：2019-12-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Hsing Chen ,  Yu-Ming Hsu ,  Yu-Chi Wang ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, in which the buffer layer includes a first buffer layer and a second buffer layer. Preferably, the first buffer layer includes a first layer of the first buffer layer comprising AlyGa1-yN on the substrate and a second layer of the first buffer layer comprising AlxGa1-xN on the first layer of the first buffer layer. The second buffer layer includes a first layer of the second buffer layer comprising AlwGa1-wN on the first buffer layer and a second layer of the second buffer layer comprising AlzGa1-zN on the first layer of the second buffer layer, in which x>z>y>w.