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    Semiconductor structure
    51.
    发明授权
    Semiconductor structure 有权
    半导体结构

    公开(公告)号：US09136375B2

    公开(公告)日：2015-09-15

    申请号：US14085939

    申请日：2013-11-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chiu-Te Lee ,  Ming-Shun Hsu ,  Ke-Feng Lin ,  Chih-Chung Wang ,  Hsuan-Po Liao ,  Shih-Teng Huang ,  Shu-Wen Lin ,  Su-Hwa Tsai ,  Shih-Yin Hsiao

    IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10

    CPC classification number: H01L29/7816 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1095

    Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

    Abstract translation: 提供半导体结构。 半导体结构包括衬底，在衬底中形成的深阱，在深阱中形成的第一阱和第二阱，形成在衬底上并设置在第一阱和第二阱之间的栅电极，第一隔离， 和第二个隔离。 第二口井与第一口井隔开。 第一隔离件从衬底的表面向下延伸并且设置在栅电极和第二阱之间。 第二隔离件从衬底的表面向下延伸并与第一阱相邻。 第一隔离深度与第二隔离深度之比小于1。

    SEMICONDUCTOR STRUCTURE
    52.
    发明申请
    SEMICONDUCTOR STRUCTURE 有权
    半导体结构

    公开(公告)号：US20150137228A1

    公开(公告)日：2015-05-21

    申请号：US14085939

    申请日：2013-11-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chiu-Te Lee ,  Ming-Shun Hsu ,  Ke-Feng Lin ,  Chih-Chung Wang ,  Hsuan-Po Liao ,  Shih-Teng Huang ,  Shu-Wen Lin ,  Su-Hwa Tsai ,  Shih-Yin Hsiao

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L27/088

    CPC classification number: H01L29/7816 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1095

    Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

    Abstract translation: 提供半导体结构。 半导体结构包括衬底，在衬底中形成的深阱，在深阱中形成的第一阱和第二阱，形成在衬底上并设置在第一阱和第二阱之间的栅电极，第一隔离， 和第二个隔离。 第二口井与第一口井隔开。 第一隔离件从衬底的表面向下延伸并且设置在栅电极和第二阱之间。 第二隔离件从衬底的表面向下延伸并与第一阱相邻。 第一隔离深度与第二隔离深度之比小于1。

    Transistor structure
    56.
    发明授权
    Transistor structure 有权

    公开(公告)号：US10373872B2

    公开(公告)日：2019-08-06

    申请号：US15813945

    申请日：2017-11-15

    Applicant: United Microelectronics Corp.

    Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

    IPC: H01L29/06 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8249

    Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.

    Doping method for semiconductor device
    57.
    发明授权
    Doping method for semiconductor device 有权

    公开(公告)号：US10354878B2

    公开(公告)日：2019-07-16

    申请号：US15402970

    申请日：2017-01-10

    Applicant: United Microelectronics Corp.

    Inventor： Kai-Kuen Chang ,  Shih-Yin Hsiao

    IPC: H01L29/10 ,  H01L21/265 ,  H01L21/266 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A doping method for a semiconductor device including the following steps is provided. A substrate is provided. The substrate has a channel region. The channel region includes a first edge region, a second edge region and a center region in a channel width direction substantially perpendicular to a channel length direction, and the center region is located between the first edge region and the second edge region. A first doping process is performed on the first edge region, the second edge region and the center region by using a first conductive type dopant. A second doping process is performed on the center region by using a second conductive type dopant.

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