公开(公告)号：US20110075504A1

公开(公告)日：2011-03-31

申请号：US12566862

申请日：2009-09-25

申请人： Yuen H. Chan ,  Louis C. Hsu ,  Xu Ouyang ,  Robert C. Wong

发明人： Yuen H. Chan ,  Louis C. Hsu ,  Xu Ouyang ,  Robert C. Wong

IPC分类号： G11C8/16 ,  G11C11/00

CPC分类号： G11C8/16 ,  G11C11/412

摘要： A static random access memory (SRAM) cell includes a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio. A static random access memory (SRAM) array includes a plurality of SRAM cells, an SRAM cell including a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio.

摘要翻译： 静态随机存取存储器（SRAM）单元包括第一读取端口，第一读取端口具有第一β比率; 和写入端口，所述写入端口具有基本上低于所述第一β比率的第二β比率。 静态随机存取存储器（SRAM）阵列包括多个SRAM单元，包括第一读取端口的SRAM单元，第一读取端口具有第一β比率; 和写入端口，所述写入端口具有基本上低于所述第一β比率的第二β比率。

公开(公告)号：US07906428B2

公开(公告)日：2011-03-15

申请号：US12121216

申请日：2008-05-15

申请人： Lawrence A. Clevenger ,  Timothy Joseph Dalton ,  Louis C. Hsu ,  Conal Eugene Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Timothy Joseph Dalton ,  Louis C. Hsu ,  Conal Eugene Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.

摘要翻译： 本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。 本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。 具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

公开(公告)号：US07772649B2

公开(公告)日：2010-08-10

申请号：US12036325

申请日：2008-02-25

申请人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  Carl Radens ,  William Tonti

发明人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  Carl Radens ,  William Tonti

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78648

摘要： A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.

摘要翻译： 将掩模层施加在顶部半导体层上并且被图案化以在开口中暴露浅沟槽隔离结构以及要在其中形成第一源极/漏极区域和主体的顶部半导体区域的一部分。 将离子注入到开口区域内的埋入绝缘体层的一部分中以形成损坏的埋层绝缘体区域。 去除浅沟槽隔离结构，并且损坏的埋层绝缘体区域被选择性地蚀刻到未损坏的埋入绝缘体部分以形成空腔。 在顶部半导体区域的侧壁和暴露的底表面上形成介电层，并且形成填充空腔的背栅。 形成接触以向后栅极提供电偏压，使得主体和第一源极/漏极区域的电势被电调制。

公开(公告)号：US07692308B2

公开(公告)日：2010-04-06

申请号：US12256735

申请日：2008-10-23

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L29/40

CPC分类号： H01L21/7682 ,  H01L21/76808 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The circuit structure includes at least two generally parallel conductor structures, and a plurality of substantially horizontal layers of layer dielectric material interspersed with substantially horizontally extending relatively low dielectric constant (low-k) volumes. The substantially horizontal layers and the substantially horizontally extending volumes are generally interposed between the at least two generally parallel conductor structures. Also included are a plurality of substantially vertically extending relatively low-k volumes sealed within the substantially horizontal layers and the substantially horizontally extending volumes between the at least two generally parallel conductor structures. The substantially vertically extending relatively low-k volumes and the substantially horizontally extending relatively low-k volumes reduce parasitic capacitance between the at least two generally parallel conductor structures as compared to an otherwise comparable microelectronic circuit not including the relatively low-k volumes.

摘要翻译： 电路结构包括至少两个大致平行的导体结构，以及多个基本上水平的层介质材料层，散布着基本上水平延伸的相对较低的介电常数（低k）体积。 基本水平的层和基本上水平延伸的体积通常介于至少两个大致平行的导体结构之间。 还包括在基本水平的层内密封的多个基本上垂直延伸的相对低k的体积，以及在至少两个大致平行的导体结构之间的基本水平延伸的体积。 与不包括相对低k体积的其他可比较的微电子电路相比，基本垂直延伸的相对低k体积和基本水平延伸的相对低k体积减小了至少两个大致平行的导体结构之间的寄生电容。

公开(公告)号：US07660350B2

公开(公告)日：2010-02-09

申请号：US12218272

申请日：2008-07-14

申请人： Louis C. Hsu ,  Brian L. Ji ,  James S. Mason ,  Karl D. Selander ,  Michael A. Soma ,  Steven J. Zier

发明人： Louis C. Hsu ,  Brian L. Ji ,  James S. Mason ,  Karl D. Selander ,  Michael A. Soma ,  Steven J. Zier

IPC分类号： H04B3/46

CPC分类号： H04L25/085 ,  H03F1/3241 ,  H04L25/0278 ,  H04L25/0292 ,  H04L25/03343 ,  H04L25/061 ,  H04L2025/0349 ,  H04L2025/03566 ,  H04L2025/03617 ,  H04L2025/03808

摘要： A data receiver is provided which is operable to receive a signal controllably pre-distorted and transmitted by a transmitter, to generate information for adjusting the pre-distortion applied to the signal transmitted by the transmitter, and to transmit the information to the transmitter. The receiver is further operable to perform adaptive equalization to receive the signal transmitted by the transmitter.

摘要翻译： 提供了一种数据接收器，其可操作以接收由发射机可控地预失真和发送的信号，以产生用于调整应用于由发射机发送的信号的预失真的信息，并将该信息发送到发射机。 接收机还可操作以执行自适应均衡以接收由发射机发送的信号。

公开(公告)号：US20090200598A1

公开(公告)日：2009-08-13

申请号：US12027496

申请日：2008-02-07

申请人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

发明人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/7881

摘要： A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.

摘要翻译： 具有增强的电容耦合系数比（CCCR）的闪速存储器结构可以以自对准方式制造，同时使用半导体衬底，该半导体衬底具有相对于围绕有源区域的隔离区域在孔内凹入的有源区域 。 闪速存储器结构包括不在隔离区上方升起的浮栅，并且优选地由具有U形的单层组成。 U形有助于增强电容耦合系数比。

公开(公告)号：US07528065B2

公开(公告)日：2009-05-05

申请号：US11333068

申请日：2006-01-17

申请人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis C. Hsu ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis C. Hsu ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L27/1203 ,  H01L21/28114 ,  H01L21/823456 ,  H01L21/84 ,  H01L29/42376 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.

摘要翻译： 晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅电极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。

公开(公告)号：US20090072410A1

公开(公告)日：2009-03-19

申请号：US12256735

申请日：2008-10-23

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L23/52

CPC分类号： H01L21/7682 ,  H01L21/76808 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The circuit structure includes at least two generally parallel conductor structures, and a plurality of substantially horizontal layers of layer dielectric material interspersed with substantially horizontally extending relatively low dielectric constant (low-k) volumes. The substantially horizontal layers and the substantially horizontally extending volumes are generally interposed between the at least two generally parallel conductor structures. Also included are a plurality of substantially vertically extending relatively low-k volumes sealed within the substantially horizontal layers and the substantially horizontally extending volumes between the at least two generally parallel conductor structures. The substantially vertically extending relatively low-k volumes and the substantially horizontally extending relatively low-k volumes reduce parasitic capacitance between the at least two generally parallel conductor structures as compared to an otherwise comparable microelectronic circuit not including the relatively low-k volumes.

摘要翻译： 电路结构包括至少两个大致平行的导体结构，以及多个基本上水平的层介质材料层，散布着基本上水平延伸的相对较低的介电常数（低k）体积。 基本水平的层和基本上水平延伸的体积通常介于至少两个大致平行的导体结构之间。 还包括在基本水平的层内密封的多个基本上垂直延伸的相对低k的体积，以及在至少两个大致平行的导体结构之间的基本水平延伸的体积。 与不包括相对低k体积的其他可比较的微电子电路相比，基本垂直延伸的相对低k体积和基本水平延伸的相对低k体积减小了至少两个大致平行的导体结构之间的寄生电容。

公开(公告)号：US20090072290A1

公开(公告)日：2009-03-19

申请号：US11857770

申请日：2007-09-19

申请人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  William Tonti

发明人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  William Tonti

IPC分类号： H01L21/70 ,  H01L27/108

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10861 ,  H01L28/60

摘要： An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.

摘要翻译： 孤立的浅沟槽隔离部分形成在绝缘体上半导体衬底的顶部半导体部分以及浅沟槽隔离结构中。 环形形状的沟槽形成在掺杂顶部半导体部分周围，并填充有诸如掺杂多晶硅的导电材料。 隔离的浅沟槽隔离部分和由导电材料的环限定的掩​​埋绝缘体层的部分被蚀刻以形成空腔。 在空腔内的暴露的半导体表面上和掺杂的顶部半导体部分之上形成电容器电介质。 形成在沟槽中并且在掺杂顶部半导体部分上方的导电材料部分构成电容器的内部电极，而导电材料的环，掺杂的顶部半导体部分和与电容器电介质邻接的手柄衬底的一部分构成一个 第二电极。

公开(公告)号：US07439172B2

公开(公告)日：2008-10-21

申请号：US11623478

申请日：2007-01-16

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/7682

摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.

摘要翻译： 一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。 具有多个互连开口和多个间隙开口的第一介电层形成在第一布线层的上方。 互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。 包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。 具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。