公开(公告)号：US07075820B2

公开(公告)日：2006-07-11

申请号：US10845403

申请日：2004-05-14

申请人： Takashi Yamada ,  Fumio Horiguchi ,  Takashi Ohsawa ,  Yoshihisa Iwata ,  Yoshiaki Asao

发明人： Takashi Yamada ,  Fumio Horiguchi ,  Takashi Ohsawa ,  Yoshihisa Iwata ,  Yoshiaki Asao

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： H01L27/108 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/1203 ,  H01L29/7841 ,  H01L29/785

摘要： A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.

摘要翻译： 半导体存储器件包括多个MIS晶体管，其布置在形成在SOI衬底上的第一字线和位线的交点处，并且每个配置存储器单元。 多个MIS晶体管中的每一个包括形成在绝缘膜上的半导体层中并设置为电浮置状态的沟道体，与半导体层中的沟道体接触形成并布置在第一字线中的第一延伸区域 形成在沟道体上的栅极绝缘膜，形成在栅极绝缘膜上并电连接到第一字线中的相应一个的栅极电极以及在半导体层中分别形成在位线方向上的源极和漏极区域 夹住通道体。

公开(公告)号：US06960815B2

公开(公告)日：2005-11-01

申请号：US10379656

申请日：2003-03-06

申请人： Hiroaki Yoda ,  Yoshiaki Asao ,  Tomomasa Ueda ,  Minoru Amano ,  Tatsuya Kishi ,  Keiji Hosotani ,  Junichi Miyamoto

发明人： Hiroaki Yoda ,  Yoshiaki Asao ,  Tomomasa Ueda ,  Minoru Amano ,  Tatsuya Kishi ,  Keiji Hosotani ,  Junichi Miyamoto

IPC分类号： G11C11/15 ,  G11C11/00 ,  G11C11/16 ,  H01L21/00 ,  H01L21/8246 ,  H01L27/00 ,  H01L27/105 ,  H01L27/22 ,  H01L29/82 ,  H01L43/00 ,  H01L43/08

CPC分类号： G11C11/16 ,  B82Y10/00 ,  H01L27/228 ,  H01L43/08

摘要： A magnetic memory device includes first wiring which runs in the first direction, second wiring which runs in the second direction, a magneto-resistance element which is arranged at an intersection between the first and second wirings, a first yoke main body which covers at least either of the lower surface and two side surfaces of the first wring, a second yoke main body which covers at least either of the upper surface and two side surfaces of the second wiring, first and second yoke tips which are arranged on two sides of the magneto-resistance element in the first direction at an interval from the magneto-resistance element, and third and fourth yoke tips which are arranged on two sides of the magneto-resistance element in the second direction at an interval from the magneto-resistance element.

摘要翻译： 磁存储装置包括沿第一方向延伸的第一布线，沿第二方向延伸的第二布线，布置在第一布线和第二布线之间的交叉点处的磁阻元件，至少覆盖第一布线 第一绕线的下表面和两个侧表面中的任一个，覆盖第二布线的上表面和两个侧表面中的至少一个的第二轭主体，布置在第二布线的两侧上的第一和第二轭尖 磁阻元件以与磁阻元件间隔的方式在第一方向上，以及第三和第四磁轭尖端，其在与磁阻元件间隔开的第二方向上布置在磁阻元件的两侧。

公开(公告)号：US20050195673A1

公开(公告)日：2005-09-08

申请号：US10617666

申请日：2003-07-14

申请人： Yoshiaki Asao ,  Yoshihisa Iwata

发明人： Yoshiaki Asao ,  Yoshihisa Iwata

IPC分类号： G11C7/00

CPC分类号： G11C11/1673 ,  G11C11/1659 ,  G11C11/1675

摘要： A magnetic random access memory includes memory cells each including a TMR element and a selection element, and a read circuit which reads storage information from the TMR element by applying read voltage to a selected one of the memory cells and causing a current to flow through the TMR element via the selection element. The read circuit includes a voltage setting section used to apply voltage which makes a resistance variation rate of the TMR element substantially equal to half a resistance variation rate thereof obtained when 0 V is applied across the TMR element to the TMR element at the information read time.

摘要翻译： 磁性随机存取存储器包括各自包括TMR元件和选择元件的存储单元，以及读取电路，其通过将读取电压施加到所选择的一个存储器单元并且使电流流过所述存储器单元而从TMR元件读取存储信息 TMR元素通过选择元素。 读取电路包括用于施加电压的电压设定部分，其使TMR元件的电阻变化率基本上等于当在信息读取时间TMR元件向TMR元件施加0V时获得的电阻变化率的一半 。

公开(公告)号：US06927468B2

公开(公告)日：2005-08-09

申请号：US10379915

申请日：2003-03-06

申请人： Hiroaki Yoda ,  Yoshiaki Asao ,  Tomomasa Ueda ,  Junichi Miyamoto ,  Tatsuya Kishi ,  Minoru Amano ,  Takeshi Kajiyama ,  Hisanori Aikawa

发明人： Hiroaki Yoda ,  Yoshiaki Asao ,  Tomomasa Ueda ,  Junichi Miyamoto ,  Tatsuya Kishi ,  Minoru Amano ,  Takeshi Kajiyama ,  Hisanori Aikawa

IPC分类号： G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  H01L29/82

CPC分类号： G11C11/16

摘要： A write line is covered with a yoke material. The recording layer of an MTJ element is exchange-coupled to the yoke material. The total magnetic volume ΣMsi×ti of the recording layer of the MTJ element and a portion of the yoke material that is exchange-coupled to the recording layer is smaller than the magnetic volume ΣMsi′×ti′ of the remaining portion of the yoke material that covers the write line.

摘要翻译： 写线用轭材料覆盖。 MTJ元件的记录层与磁轭材料交换耦合。 MTJ元件的记录层的总磁体体积SigmaMsixti和与记录层交换耦合的磁轭材料的一部分小于磁轭材料的剩余部分的磁体积SigmaMsi'xti' 写行。

公开(公告)号：US20050087786A1

公开(公告)日：2005-04-28

申请号：US10971096

申请日：2004-10-25

申请人： Yoshiaki Asao

发明人： Yoshiaki Asao

IPC分类号： G11C11/15 ,  G11C11/00 ,  H01L21/00 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L29/76 ,  H01L29/78 ,  H01L31/062 ,  H01L31/119 ,  H01L43/08

CPC分类号： H01L43/08 ,  B82Y10/00 ,  H01L27/224 ,  H01L27/228

摘要： A data selection line (write line) is disposed right on a MTJ element. Upper and side surfaces of the data selection line are coated with yoke materials which have a high permeability. The yoke materials are separated from each other by a barrier layer. Similarly, a write word line is disposed right under the MTJ element. The lower and side surfaces of the write word line are also coated with the yoke materials which have the high permeability. The yoke materials on the lower and side surfaces of the write word line are also separated from each other by the barrier layer.

公开(公告)号：US06873023B2

公开(公告)日：2005-03-29

申请号：US10418047

申请日：2003-04-18

申请人： Yoshiaki Asao ,  Yoshihisa Iwata ,  Yoshiaki Saito ,  Hiroaki Yoda ,  Tomomasa Ueda ,  Minoru Amano ,  Shigeki Takahashi ,  Tatsuya Kishi

发明人： Yoshiaki Asao ,  Yoshihisa Iwata ,  Yoshiaki Saito ,  Hiroaki Yoda ,  Tomomasa Ueda ,  Minoru Amano ,  Shigeki Takahashi ,  Tatsuya Kishi

IPC分类号： G11C11/16 ,  H01L43/00

CPC分类号： G11C11/16

摘要： A write word line is disposed right under an MTJ element. The write word line extends in an X direction, and a lower surface of the line is coated with a yoke material which has a high permeability. A data selection line (read/write bit line) is disposed right on the MTJ element. A data selection line extends in a Y direction intersecting with the X direction, and an upper surface of the line is coated with the yoke material which has the high permeability. At a write operation time, a magnetic field generated by a write current flowing through a write word line B and data selection line functions on the MTJ element by the yoke material with good efficiency.

摘要翻译： 写字线被放置在MTJ元素的正下方。 写字线在X方向上延伸，并且线的下表面涂覆有具有高磁导率的磁轭材料。 数据选择线（读/写位线）设置在MTJ元件上。 数据选择线在与X方向交叉的Y方向上延伸，并且线的上表面涂覆有具有高磁导率的磁轭材料。 在写操作时刻，通过写入字线B和数据选择线产生的写入电流产生的磁场通过磁轭材料以良好的效率在MTJ元件上起作用。

公开(公告)号：US06831857B2

公开(公告)日：2004-12-14

申请号：US10329417

申请日：2002-12-27

申请人： Minoru Amano ,  Tatsuya Kishi ,  Hiroaki Yoda ,  Yoshiaki Saito ,  Shigeki Takahashi ,  Tomomasa Ueda ,  Katsuya Nishiyama ,  Yoshiaki Asao ,  Yoshihisa Iwata

发明人： Minoru Amano ,  Tatsuya Kishi ,  Hiroaki Yoda ,  Yoshiaki Saito ,  Shigeki Takahashi ,  Tomomasa Ueda ,  Katsuya Nishiyama ,  Yoshiaki Asao ,  Yoshihisa Iwata

IPC分类号： G11C1115

CPC分类号： G11C11/15

摘要： A highly reliable magnetic memory exhibits enhanced data-holding stability at high storage density in a storage layer of a magnetoresistive effect element used for memory cells. A magnetic memory includes a memory cell array having first wirings, second wirings intersecting the first wirings and memory cells each provided at an intersection area of the corresponding first and second wirings. Each memory cell is selected when the corresponding first and second wirings are selected. Each memory cell includes a magnetoresistive effect element having a storage layer in which data is stored by magnetic fields generated when current flows the selected first and second wirings, a first magnetic member, having two ends, provided as partially surrounding each first wiring and the two ends being situated in a direction of easy axis of magnetization, to form a closed-loop magnetic circuitry with the storage layer, and a second magnetic member, having two ends, provided as partially surrounding each second wiring and the two ends being situated in a direction of hard axis of magnetization, to amplify magnetic fields applied to the storage layer in the direction of hard axis of magnetization. Each end of the first magnetic member is situated as closer than each end of the second magnetic member to the storage layer.

公开(公告)号：US08981446B2

公开(公告)日：2015-03-17

申请号：US14018337

申请日：2013-09-04

申请人： Takashi Nakazawa ,  Yoshiaki Asao ,  Takeshi Kajiyama ,  Kenji Noma

发明人： Takashi Nakazawa ,  Yoshiaki Asao ,  Takeshi Kajiyama ,  Kenji Noma

IPC分类号： H01L27/108 ,  H01L21/8244 ,  G11C11/00 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1655 ,  H01L27/2463 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： According to one embodiment, a magnetic memory including an isolation region with an insulator in a trench is disclosed. The isolation region defines active areas extending in a 1st direction and having 1st and 2nd active areas, an isolation region extending in a 2nd direction perpendicular to the 1st direction exists between the 1st and 2nd active areas. 1st and 2nd word lines extending in the 2nd direction are buried in a surface of semiconductor substrate. 1st and 2nd select transistors connected to the word lines are on the 1st active area. 1st and 2nd variable resistance elements connected to drain regions of the 1st and 2nd select transistors are on the 1st active area.

摘要翻译： 根据一个实施例，公开了一种包括在沟槽中具有绝缘体的隔离区的磁存储器。 隔离区域限定在第一方向上延伸并且具有第一和第二有源区域的有源区域，在第一和第二有效区域之间存在沿垂直于第一方向的第二方向延伸的隔离区域。 在第二方向上延伸的第一和第二字线被埋在半导体衬底的表面中。 连接到字线的第一和第二选择晶体管在第一有效区域。 连接到第一和第二选择晶体管的漏极区的第一和第二可变电阻元件在第一有效区上。

公开(公告)号：US08779410B2

公开(公告)日：2014-07-15

申请号：US13355692

申请日：2012-01-23

申请人： Motoyuki Sato ,  Yoshiaki Asao ,  Takashi Obara ,  Takashi Nakazawa

发明人： Motoyuki Sato ,  Yoshiaki Asao ,  Takashi Obara ,  Takashi Nakazawa

IPC分类号： H01L21/00 ,  H01L29/06 ,  H01L27/22

CPC分类号： H01L27/228

摘要： According to one embodiment, a resistance change memory includes resistance change elements, vias and sidewall insulating layers, the elements and the vias provided alternately in a first direction and a second direction orthogonal to the first direction, and the sidewall insulating layers provided on sidewalls of the elements. The elements are provided in a lattice pattern having a constant pitch. A thickness of each of the sidewall insulating layers in a direction orthogonal to the sidewalls is a value for contacting the sidewall insulating layers each other or more to form holes between the sidewall insulating layers. The vias are provided in the holes respectively.

摘要翻译： 根据一个实施例，电阻变化存储器包括电阻变化元件，通路和侧壁绝缘层，沿与第一方向正交的第一方向和第二方向上交替设置的元件和通孔，以及设置在第二方向上的侧壁绝缘层 元素。 元件以具有恒定间距的格子图案提供。 每个侧壁绝缘层在与侧壁正交的方向上的厚度是用于使侧壁绝缘层彼此接触或接触以在侧壁绝缘层之间形成孔的值。 通孔分别设置在孔中。

公开(公告)号：US08542519B2

公开(公告)日：2013-09-24

申请号：US13035168

申请日：2011-02-25

申请人： Yoshiaki Asao ,  Takeshi Kajiyama ,  Kuniaki Sugiura

发明人： Yoshiaki Asao ,  Takeshi Kajiyama ,  Kuniaki Sugiura

IPC分类号： G11C11/02

CPC分类号： H01L29/82

摘要： According to one embodiment, a semiconductor memory device is disclosed. The device includes MOSFET1 and MOSFET2 arranged in a first direction, variable resistive element (hereafter R1) above MOSFET1 and MOSFET2, a lower end of the R1 being connected to drains of MOSFET1 and MOSFET2, MOSFET3 and MOSFET4 arranged in the first direction, variable resistive element (hereafter R2) above MOSFET3 and MOSFET4, and a lower end of the R2 being connected to drains of MOSFET3 and MOSFET4. The device further includes first wiring line extending in the first direction and connected to sources of MOSFET1 and MOSFET2, second wiring line extending in the first direction and connected to sources of MOSFET3 and MOSFET4, upper electrode connecting upper end of the R1 and upper end of the R2, and third wiring line extending in the first direction and connected to the upper electrode.

摘要翻译： 根据一个实施例，公开了一种半导体存储器件。 该器件包括在第一方向上布置的MOSFET1和MOSFET2，MOSFET1和MOSFET2上方的可变电阻元件（以下称为R1），R1的下端连接到沿第一方向布置的MOSFET1和MOSFET2，MOSFET3和MOSFET4的漏极，可变电阻 元件（以下称为R2），MOSFET3和MOSFET4之上，R2的下端连接到MOSFET3和MOSFET4的漏极。 该器件还包括沿第一方向延伸并连接到MOSFET1和MOSFET2的源极的第一布线，第二布线沿第一方向延伸并连接到MOSFET3和MOSFET4的源极，上电极连接R1的上端和上端 R2和第三布线沿第一方向延伸并连接到上电极。