公开(公告)号：US07683422B2

公开(公告)日：2010-03-23

申请号：US11464324

申请日：2006-08-14

申请人： Woon-Kyung Lee ,  Jeong-Hyuk Choi ,  Jai-Hyuk Song

发明人： Woon-Kyung Lee ,  Jeong-Hyuk Choi ,  Jai-Hyuk Song

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Non-volatile memory devices include memory cells therein with reduced cell-to-cell coupling capacitance. These memory cells include floating gate electrodes with open-ended wraparound shapes that operate to reduce the cell-to-cell coupling capacitance in a bit line direction, while still maintaining a high coupling ratio between control and floating gate electrodes within each memory cell.

摘要翻译： 非易失性存储器件包括其中具有减小的单元到单元耦合电容的存储单元。 这些存储单元包括具有开口环绕形状的浮动栅极电极，其操作以在位线方向上减小电池到电池耦合电容，同时仍保持每个存储单元内的控制和浮置栅电极之间的高耦合比。

公开(公告)号：US07670904B2

公开(公告)日：2010-03-02

申请号：US11651538

申请日：2007-01-10

申请人： Woon-Kyung Lee ,  Jong-Kwang Lim

发明人： Woon-Kyung Lee ,  Jong-Kwang Lim

IPC分类号： H01L21/336

CPC分类号： H01L27/11531 ,  H01L27/105 ,  H01L27/11526

摘要： A method for fabricating a nonvolatile memory device comprises providing a substrate, forming an insulating layer and a conductive layer on the substrate, forming an electrical connection path out of a portion of the conductive layer, through which the conductive layer is electrically connected to the substrate, and gate patterning the insulating layer and the conductive layer.

摘要翻译： 一种用于制造非易失性存储器件的方法包括在衬底上提供衬底，形成绝缘层和导电层，在导电层的一部分中形成电连接路径，导电层通过该导电层电连接到衬底 ，并且对图案化绝缘层和导电层的栅极。

公开(公告)号：US20100020617A1

公开(公告)日：2010-01-28

申请号：US12480352

申请日：2009-06-08

申请人： Dong-Yean Oh ,  Woon-Kyung Lee

发明人： Dong-Yean Oh ,  Woon-Kyung Lee

IPC分类号： G11C16/06 ,  G11C7/00

CPC分类号： G11C16/3454 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11551 ,  H01L27/11556

摘要： A nonvolatile semiconductor memory device including a vertical array structure comprised of bit lines and source lines arranged in the same direction as the bit lines, each source lines corresponding to the bit lines and memory cell strings vertically formed between each pair of the bit lines and source lines. Multiple strings of memory cells can be stacked in the vertical direction, and adjacent memory cell strings may share bit line or source line.

摘要翻译： 一种非易失性半导体存储器件，包括垂直阵列结构，其包括与位线相同方向布置的位线和源极线，每个源极线对应于在每对位线和源极之间垂直形成的位线和存储单元串 线条。 多个存储单元串可以在垂直方向堆叠，并且相邻的存储单元串可以共享位线或源极线。

公开(公告)号：US20090287879A1

公开(公告)日：2009-11-19

申请号：US12424135

申请日：2009-04-15

申请人： Dong-Yean Oh ,  Woon-Kyung Lee ,  Seung-Chul Lee

发明人： Dong-Yean Oh ,  Woon-Kyung Lee ,  Seung-Chul Lee

IPC分类号： G06F12/00 ,  G11C16/04 ,  G11C16/06 ,  G06F12/02

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3454

摘要： An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.

摘要翻译： 集成电路包括一个包括串选择晶体管SST的NAND串和设置在串联存储单元MC的任一端的接地选择晶体管GST。 每个存储器存储单元是具有浮置栅极的存储晶体管，并且串选择晶体管SST和接地选择晶体管GST中的至少一个是具有浮置栅极的存储晶体管。 可编程串选择晶体管SST和接地选择晶体管GST的阈值电压Vth是可变的并且用户可控，并且不需要在制造期间通过注入建立。 存储器块中的每个可编程串选择晶体管SST和接地选择晶体管GST可用于存储随机数据，从而增加闪存器件的存储器存储容量。

公开(公告)号：US20090230457A1

公开(公告)日：2009-09-17

申请号：US12381380

申请日：2009-03-11

申请人： Jin-Sung Lee ,  Woon-Kyung Lee

发明人： Jin-Sung Lee ,  Woon-Kyung Lee

IPC分类号： H01L29/792 ,  H01L27/088 ,  H01L29/06

CPC分类号： H01L27/11521 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573

摘要： A semiconductor device includes a plurality of transistors disposed on a semiconductor substrate, a device isolation layer disposed around the transistors, a guard ring disposed to surround the device isolation layer and the transistors, and a guard region disposed between adjacent transistors.

摘要翻译： 半导体器件包括设置在半导体衬底上的多个晶体管，围绕晶体管设置的器件隔离层，设置成围绕器件隔离层和晶体管的保护环以及设置在相邻晶体管之间的保护区。

公开(公告)号：US07579244B2

公开(公告)日：2009-08-25

申请号：US11455888

申请日：2006-06-20

申请人： Woon-Kyung Lee

发明人： Woon-Kyung Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/11568

摘要： The present invention provides a semiconductor device in which the gate is self-aligned to the device isolation film and a fabricating method thereof. A device isolation film restricting an active region is disposed on a portion of a semiconductor substrate, and a word line is across over the device isolation film. A gate pattern is disposed between the word line and the active region, and a tunnel oxide film is disposed between the gate pattern and the active region. The gate pattern comprises a floating gate pattern, a gate interlayer dielectric film pattern and a control gate electrode pattern deposited in the respective order, and has a sidewall self-aligned to the device isolation film. To form the gate pattern having the sidewall self-aligned to the device isolation film, a gate insulation film and a gate material film are formed in the respective order on the semiconductor substrate.

摘要翻译： 本发明提供一种其中栅极与器件隔离膜自对准的半导体器件及其制造方法。 限制有源区的器件隔离膜设置在半导体衬底的一部分上，并且字线跨过器件隔离膜。 栅极图案设置在字线和有源区之间，并且隧道氧化膜设置在栅极图案和有源区之间。 栅极图案包括以相应顺序沉积的浮置栅极图案，栅极层间电介质膜图案和控制栅极电极图案，并且具有与器件隔离膜自对准的侧壁。 为了形成具有与器件隔离膜自对准的侧壁的栅极图案，在半导体衬底上分别形成栅极绝缘膜和栅极材料膜。

公开(公告)号：US20080081413A1

公开(公告)日：2008-04-03

申请号：US11647671

申请日：2006-12-29

申请人： Chang-Sub Lee ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song ,  Dong-Yean Oh

发明人： Chang-Sub Lee ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song ,  Dong-Yean Oh

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A semiconductor memory device can include select transistors and cell transistors on a semiconductor substrate. An insulation layer covers the select transistors and the cell transistors. The bit lines are in the insulation layer and are electrically connected to respective ones of the select transistors. The bit lines are arranged along at least two different parallel planes having different heights relative to the semiconductor substrate.

摘要翻译： 半导体存储器件可以包括半导体衬底上的选择晶体管和单元晶体管。 绝缘层覆盖选择晶体管和单元晶体管。 位线在绝缘层中并且电连接到相应的选择晶体管。 沿着相对于半导体衬底具有不同高度的至少两个不同的平行平面布置位线。

公开(公告)号：US20070190726A1

公开(公告)日：2007-08-16

申请号：US11699990

申请日：2007-01-31

申请人： Jai-Hyuk Song ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee

发明人： Jai-Hyuk Song ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11541

摘要： Embodiments of the invention provide a semiconductor device and a related method of fabricating a semiconductor device. In one embodiment, the invention provides a semiconductor device comprising a first gate electrode comprising a lower silicon pattern and an upper silicon pattern and disposed on an active region of a semiconductor substrate, wherein the upper silicon pattern has the same crystal structure as the lower silicon pattern and the active region is defined by a device isolation layer. The semiconductor device further comprises a gate insulating layer disposed between the active region and the first gate electrode.

摘要翻译： 本发明的实施例提供一种制造半导体器件的半导体器件和相关方法。 在一个实施例中，本发明提供一种半导体器件，其包括第一栅电极，其包括下硅图案和上硅图案，并设置在半导体衬底的有源区上，其中上硅图案具有与下硅相同的晶体结构 图案和有源区域由器件隔离层定义。 半导体器件还包括设置在有源区和第一栅电极之间的栅极绝缘层。

公开(公告)号：US07057226B2

公开(公告)日：2006-06-06

申请号：US10170393

申请日：2002-06-14

申请人： Woon-Kyung Lee

发明人： Woon-Kyung Lee

IPC分类号： H01L29/76

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/11568

摘要： The present invention provides a semiconductor device in which the gate is self-aligned to the device isolation film and a fabricating method thereof. A device isolation film restricting an active region is disposed on a portion of a semiconductor substrate, and a word line is across over the device isolation film. A gate pattern is disposed between the word line and the active region, and a tunnel oxide film is disposed between the gate pattern and the active region. The gate pattern comprises a floating gate pattern, a gate interlayer dielectric film pattern and a control gate electrode pattern deposited in the respective order, and has a sidewall self-aligned to the device isolation film. To form the gate pattern having the sidewall self-aligned to the device isolation film, a gate insulation film and a gate material film are formed in the respective order on the semiconductor substrate.

公开(公告)号：US07015087B2

公开(公告)日：2006-03-21

申请号：US11029832

申请日：2005-01-04

申请人： Sun-Young Kim ,  Woon-Kyung Lee ,  Dong-Whee Kwon

发明人： Sun-Young Kim ,  Woon-Kyung Lee ,  Dong-Whee Kwon

IPC分类号： H01L21/8234

CPC分类号： H01L21/76897 ,  H01L21/76895

摘要： A gate-contact structure and a method for forming the same are provided. The structure includes a device isolation layer pattern formed at a semiconductor substrate to define an active region; and a gate electrode and a capping pattern, which are sequentially stacked on the semiconductor substrate across the device isolation layer pattern. The capping pattern includes a first gate contact hole that exposes a top surface of the gate electrode. An interlayer insulation layer pattern including a second gate contact hole is disposed to cover an entire surface of the semiconductor substrate including the gate electrode and the capping pattern. The second gate contact hole penetrates the first gate contact hole to expose the top surface of the gate electrode. A gate contact plug is disposed to be connected to the top surface of the gate electrode through the second gate contact hole. Accordingly, the interlayer insulation layer pattern is intervened between the gate contact plug and a sidewall of the capping pattern.