公开(公告)号：US20130168800A1

公开(公告)日：2013-07-04

申请号：US13717803

申请日：2012-12-18

申请人： Jae-Joo Shim ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Ju-Young Lim ,  Sung-Min Hwang

发明人： Jae-Joo Shim ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Ju-Young Lim ,  Sung-Min Hwang

IPC分类号： H01L29/06

CPC分类号： H01L29/0657 ,  H01L27/0207 ,  H01L27/1157 ,  H01L27/11582

摘要： Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.

摘要翻译： 提供了包括设置在基板上的第一和第二隔离图案的半导体器件。 交替层叠的层间绝缘图案和导电图案设置在第一和第二隔离图案之间的基板的表面上。 支撑图案穿透导电图案和层间绝缘图案，并且具有比第一和第二隔离图案更小的宽度。 第一和第二垂直结构设置在第一隔离和支撑图案之间并且穿透导电图案和层间绝缘图案。 第二垂直结构设置在第二隔离图案和支撑图案之间并且穿透导电图案和层间绝缘图案。 支撑图案的顶表面和底表面之间的距离大于支撑图案的底表面和基底表面之间的距离。

公开(公告)号：US07851304B2

公开(公告)日：2010-12-14

申请号：US11641869

申请日：2006-12-20

申请人： Woon-Kyung Lee ,  Jeong-Hyuk Choi

发明人： Woon-Kyung Lee ,  Jeong-Hyuk Choi

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  Y10S438/981

摘要： Provided is a nonvolatile memory device and a fabrication method. The nonvolatile memory device includes an active region defined in a semiconductor substrate, a gate insulating layer formed on the active region and a plurality of gate patterns formed on the gate insulating layer, and crossing over the active region. The gate insulating layer includes a discharge region in a predetermined portion between the gate patterns, the discharge region having a lesser thickness than that of the gate insulating layer under the gate pattern, because a thickness portion of the gate insulating layer is removed to form the discharge region.

摘要翻译： 提供了一种非易失性存储器件和制造方法。 非易失性存储器件包括限定在半导体衬底中的有源区，形成在有源区上的栅极绝缘层和形成在栅极绝缘层上并跨过有源区的多个栅极图案。 栅极绝缘层包括在栅极图案之间的预定部分中的放电区域，由于栅极绝缘层的厚度部分被去除以形成栅极绝缘层的厚度部分，所以放电区域的厚度小于栅极图案下的栅极绝缘层的厚度。 放电区域。

公开(公告)号：US20080096350A1

公开(公告)日：2008-04-24

申请号：US11641869

申请日：2006-12-20

申请人： Woon-Kyung Lee ,  Jeong-Hyuk Choi

发明人： Woon-Kyung Lee ,  Jeong-Hyuk Choi

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  Y10S438/981

摘要： Provided is a nonvolatile memory device and a fabrication method. The nonvolatile memory device includes an active region defined in a semiconductor substrate, a gate insulating layer formed on the active region and a plurality of gate patterns formed on the gate insulating layer, and crossing over the active region. The gate insulating layer includes a discharge region in a predetermined portion between the gate patterns, the discharge region having a lesser thickness than that of the gate insulating layer under the gate pattern, because a thickness portion of the gate insulating layer is removed to form the discharge region.

摘要翻译： 提供了一种非易失性存储器件和制造方法。 非易失性存储器件包括限定在半导体衬底中的有源区，形成在有源区上的栅极绝缘层和形成在栅极绝缘层上并跨过有源区的多个栅极图案。 栅极绝缘层包括在栅极图案之间的预定部分中的放电区域，由于栅极绝缘层的厚度部分被去除以形成栅极绝缘层的厚度部分，所以放电区域的厚度小于栅极图案下的栅极绝缘层的厚度。 放电区域。

公开(公告)号：US20080079038A1

公开(公告)日：2008-04-03

申请号：US11646127

申请日：2006-12-27

申请人： Tae-Kyung Kim ,  Woon-Kyung Lee

发明人： Tae-Kyung Kim ,  Woon-Kyung Lee

IPC分类号： H01L29/76

CPC分类号： H01L21/2652 ,  H01L21/28123 ,  H01L21/28238 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/42368

摘要： Methods of forming a semiconductor device include an active region and a shallow trench isolation region in a semiconductor substrate, and forming a gate insulation layer on the active region. The gate insulation layer includes a first part spaced apart from the shallow trench isolation region and a second part adjacent the shallow trench isolation region and disposed between the shallow trench isolation region and the first part, and thicker than the first part. The methods further include forming a first impurity region in the active region of the semiconductor substrate adjacent the first part, and forming a gate line on the gate insulation layer. Corresponding semiconductor devices are also disclosed.

摘要翻译： 形成半导体器件的方法包括半导体衬底中的有源区和浅沟槽隔离区，并且在有源区上形成栅极绝缘层。 栅极绝缘层包括与浅沟槽隔离区域间隔开的第一部分和与浅沟槽隔离区域相邻并且设置在浅沟槽隔离区域和第一部分之间并且比第一部分更厚的第二部分。 所述方法还包括在所述半导体衬底的与所述第一部分相邻的有源区中形成第一杂质区，以及在所述栅极绝缘层上形成栅极线。 还公开了相应的半导体器件。

公开(公告)号：US20070001212A1

公开(公告)日：2007-01-04

申请号：US11431273

申请日：2006-05-10

申请人： Woon-Kyung Lee ,  Jeong-Hyuk Choi

发明人： Woon-Kyung Lee ,  Jeong-Hyuk Choi

IPC分类号： H01L29/788 ,  H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A NAND-type memory device may include first and second selection transistors on a semiconductor substrate and a plurality of memory cell transistors coupled in series between the first and second selection transistors. A first source/drain region may be shared between the first selection transistor and a first of the memory cell transistors, and a second source/drain region may be shared between the second selection transistor and a last of the memory cell transistors. Moreover, a portion of at least one of the first and/or second source/drain regions may be recessed relative to a surface of the semiconductor substrate. Related methods are also discussed.

摘要翻译： NAND型存储器件可以包括半导体衬底上的第一和第二选择晶体管和串联耦合在第一和第二选择晶体管之间的多个存储单元晶体管。 第一源/漏区可以在第一选择晶体管和第一存储单元晶体管之间共享，并且第二源/漏区可以在第二选择晶体管和最后的存储单元晶体管之间共享。 此外，第一和/或第二源极/漏极区域中的至少一个的一部分可以相对于半导体衬底的表面凹陷。 还讨论了相关方法。

公开(公告)号：US20060231885A1

公开(公告)日：2006-10-19

申请号：US11455888

申请日：2006-06-20

申请人： Woon-Kyung Lee

发明人： Woon-Kyung Lee

IPC分类号： H01L29/76 ,  H01L29/00

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/11568

摘要： The present invention provides a semiconductor device in which the gate is self-aligned to the device isolation film and a fabricating method thereof. A device isolation film restricting an active region is disposed on a portion of a semiconductor substrate, and a word line is across over the device isolation film. A gate pattern is disposed between the word line and the active region, and a tunnel oxide film is disposed between the gate pattern and the active region. The gate pattern comprises a floating gate pattern, a gate interlayer dielectric film pattern and a control gate electrode pattern deposited in the respective order, and has a sidewall self-aligned to the device isolation film. To form the gate pattern having the sidewall self-aligned to the device isolation film, a gate insulation film and a gate material film are formed in the respective order on the semiconductor substrate.

公开(公告)号：US20050118798A1

公开(公告)日：2005-06-02

申请号：US11029832

申请日：2005-01-04

申请人： Sun-Young Kim ,  Woon-Kyung Lee ,  Dong-Whee Kwon

发明人： Sun-Young Kim ,  Woon-Kyung Lee ,  Dong-Whee Kwon

IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L29/788 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76895

摘要： A gate-contact structure and a method for forming the same are provided. The structure includes a device isolation layer pattern formed at a semiconductor substrate to define an active region; and a gate electrode and a capping pattern, which are sequentially stacked on the semiconductor substrate across the device isolation layer pattern. The capping pattern includes a first gate contact hole that exposes a top surface of the gate electrode. An interlayer insulation layer pattern including a second gate contact hole is disposed to cover an entire surface of the semiconductor substrate including the gate electrode and the capping pattern. The second gate contact hole penetrates the first gate contact hole to expose the top surface of the gate electrode. A gate contact plug is disposed to be connected to the top surface of the gate electrode through the second gate contact hole. Accordingly, the interlayer insulation layer pattern is intervened between the gate contact plug and a sidewall of the capping pattern.

摘要翻译： 提供了栅极接触结构及其形成方法。 该结构包括形成在半导体衬底上以限定有源区的器件隔离层图案; 以及栅电极和封盖图案，其跨越器件隔离层图案依次堆叠在半导体衬底上。 封盖图案包括暴露栅电极的顶表面的第一栅极接触孔。 设置包括第二栅极接触孔的层间绝缘层图案以覆盖包括栅电极和封盖图案的半导体衬底的整个表面。 第二栅极接触孔穿过第一栅极接触孔以暴露栅电极的顶表面。 栅极接触插头设置成通过第二栅极接触孔连接到栅电极的顶表面。 因此，层间绝缘层图案介于栅极接触插塞和封盖图案的侧壁之间。

公开(公告)号：US06531360B2

公开(公告)日：2003-03-11

申请号：US09948424

申请日：2001-09-07

申请人： Woon-Kyung Lee

发明人： Woon-Kyung Lee

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： A method of manufacturing a flash memory device is characterized by preventing photoresist patterns from being formed directly on or removed directly from a surface of the substrate or the dielectric layer. This is accomplished by separately forming a control gate layer of transistors in a cell area of the substrate and a gate layer of transistors in a peripheral circuit area of the substrate. The method of the present invention includes the steps of forming in a peripheral circuit area of the substrate a gate insulating layer for both high and low voltage regions of the peripheral circuit area and then forming the gate conduction layer on the gate insulating layer. The method of the present invention further comprises the steps of forming in a cell area of the substrate a transistor structure composed of a tunneling gate insulating layer, a floating gate layer, a dielectric layer, and a control gate layer.

公开(公告)号：US06346733B1

公开(公告)日：2002-02-12

申请号：US09345581

申请日：1999-06-30

申请人： Woon-Kyung Lee ,  Youn-Ho Lee ,  Eui-Do Kim

发明人： Woon-Kyung Lee ,  Youn-Ho Lee ,  Eui-Do Kim

IPC分类号： H01L2976

CPC分类号： H01L27/1126 ,  G11C17/126 ,  H01L27/112 ,  Y10S438/926

摘要： A nonvolatile memory device is provided in which cell uniformity is significantly improved. The device includes a plurality of burial N+ diffusion layers extending over the surface of a semiconductor substrate. The plurality of burial N+ diffusion layers are the source/drains of cell transistors and the sub bit-lines of the memory cell array. The device additionally includes a plurality of word lines formed over the semiconductor substrate with gate dielectrics interposed therebetween. The plurality of word lines extend perpendicularly to the burial N+ diffusion layers. A plurality of select lines extend parallel to the word lines and selectively transfer external electrical signals via main bit-lines to the sub bit-lines. The main bit-lines extend parallel to said sub bit-lines. Finally, dummy lines extend parallel to the word lines in the spaces between the select lines and the adjacent word lines.

摘要翻译： 提供了一种非易失性存储器件，其中电池均匀性显着提高。 该装置包括在半导体衬底的表面上延伸的多个埋入N +扩散层。 多个埋置N +扩散层是单元晶体管的源极/漏极和存储单元阵列的子位线。 该器件还包括形成在半导体衬底上的多个字线，其间插入栅极电介质。 多个字线垂直于埋藏的N +扩散层延伸。 多个选择线平行于字线延伸，并且经由主位线选择性地将外部电信号传送到子位线。 主位线平行于所述子位线延伸。 最后，虚拟线平行于选择线和相邻字线之间的空格中的字线延伸。

公开(公告)号：US09112045B2

公开(公告)日：2015-08-18

申请号：US13775833

申请日：2013-02-25

申请人： Ju-Hyung Kim ,  Chang-Seok Kang ,  Woon-Kyung Lee

发明人： Ju-Hyung Kim ,  Chang-Seok Kang ,  Woon-Kyung Lee

IPC分类号： H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L27/115

CPC分类号： H01L29/792 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/7926

摘要： A nonvolatile memory device comprises a channel pattern, a first interlayer dielectric film and a second interlayer dielectric film spaced apart from each other and stacked over each other, a gate pattern disposed between the first interlayer dielectric film and the second interlayer dielectric film, a trap layer disposed between the gate pattern and the channel pattern and a charge spreading inhibition layer disposed between the channel pattern and the first interlayer dielectric film and between the channel pattern and the second interlayer dielectric film. The charge spreading inhibition layer may include charges inside or on its surface. The charge spreading inhibition layer includes at least one of a metal oxide film or a metal nitride film or a metal oxynitride film having a greater dielectric constant than a silicon oxide film.

摘要翻译： 非易失性存储器件包括彼此间隔开并且彼此堆叠的沟道图案，第一层间电介质膜和第二层间电介质膜，布置在第一层间电介质膜和第二层间电介质膜之间的栅极图案，阱 设置在栅极图案和沟道图案之间的层，以及设置在沟道图案和第一层间电介质膜之间以及沟道图案和第二层间电介质膜之间的电荷扩展抑制层。 电荷扩散抑制层可以包括其表面内部或其表面上的电荷。 电荷扩散抑制层包括金属氧化物膜或金属氮化物膜或具有比氧化硅膜更大的介电常数的金属氧氮化物膜中的至少一种。