Abstract:
Methods and systems for processing signals in a wireless communication system are disclosed. Aspects of the method may include estimating at a receiver, a rate at which a communication channel changes. A length of a filter used to average a noise power estimate and/or a signal power estimate may be adaptively changed based on the estimation of the rate at which the communication channel changes. The communication channel may comprise a common pilot channel (CPICH). At least a portion of a wireless signal received via the communication channel may be descrambled at the receiver to generate a plurality of descrambled bits. At least a portion of the plurality of descrambled bits may be accumulated to generate at least one in-phase (I) component and at least one quadrature (Q) component.
Abstract:
Providing and configuring communication links may include determining a usable media pair from all existing media pairs and selecting any one channel from all existing channels. The selected channel may be assigned to any one of the media pairs. Any one or any combination of media pairs may be monitored in order to detect the existence of a communication signal on any of the media pairs. Some or all of the existing media pairs may be monitored to determine which of the media pair may be capable of facilitating communication at a maximum communication speed and if not, at a reduced speed. Any selected channel may be cross-connected to any one of the existing media pairs, which may be capable of facilitating communication at the maximum or reduced communication speed.
Abstract:
Aspects of a method and system for signal processing are disclosed and may include receiving a plurality of wireless signals via a plurality of M receive antennas. Each of M phase shifters coupled to each of the M receive antennas may be set to operate in a bypass mode or with an arbitrary phase setting. Corresponding signal strengths of M signals generated when each of the M phase-shifters is coupled to each of the M receive antennas may be measured, while at least a portion of the M receive antennas are turned off. Selecting one of the M generated signals for processing without the use of an antenna switch, based on the measured signal strength. A signal strength of each of the generated M amplified signals may be measured while turning off at least one of the plurality of M receive antennas and without the use of the phase-shifters.
Abstract:
A method and system for minimizing power consumption in a communication system is provided. The method may include adjusting the supply voltage of a linear amplifier, which may be used for amplifying a RF signal, in proportion to the envelope of the baseband of the RF signal. The signals may correspond to a variety of communication protocols. For example, WCDMA, HSDPA, HSUDPA, GSM, GPRS, EDGE, WiMAX, OFDM, UWB, ZigBee, and BlueTooth. The baseband signal may be delayed by a number of samples before being input into the amplifier. The envelope may be measured by evaluating a plurality of I and Q samples from the baseband signal. The number of samples may be calculated by measuring the intermodulation distortion at the output of the amplifier. The supply voltage may be generated by a switching regulator. The method may also include adjusting a bias voltage of the amplifier in proportion to the envelope of the baseband signal, where the bias voltage may control the gain of the amplifier. The bias voltage may also be generated by a switching regulator.
Abstract:
A system for encoding data in a multilane communication channel may include at least one processor operable to generate, from existing control characters in a character set, expanded control characters utilized for controlling the data in each lane of the multilane communication channel. Each lane of the multilane communication channel may transport the data in a similar direction. The at least one processor is also operable to control at least one of the lanes of the multilane communication channel using at least one of the generated control characters. If a first control character of the existing control characters is a start-of-packet control character, the at least one processor is then operable to select a second control character from any other of the generated expanded control characters, and to indicate a start of a packet using the selected second control character for at least one of the lanes.
Abstract:
Methods and systems for calibrating a frequency of a circuit are disclosed herein and may comprise dividing a feedback frequency of an output frequency signal to generate a divided frequency signal. Open loop calibration may be performed based on a binary search of the generated divided frequency signal to generate a coarse calibrated frequency signal. Subsequently, a closed loop calibration may be performed on the coarse calibrated frequency signal to generate a fine calibrated frequency signal. A binary code may be generated utilizing the binary search of the generated divided frequency signal. Capacitance within the circuit may be adjusted based on the generated binary code. A control voltage for the circuit may be measured by closing a phase locked loop (PLL) with the circuit. If the measured control voltage is not within a determined voltage range, a calibration flag signal may be generated.
Abstract:
A method for configuring a multi-port digital subscriber line (DSL) modem, the method begins by utilizing frequency bands of a single DSL channel to support a data communication when loop length of the single DSL channel and data rate of the data communication are favorable. The method continues by utilizing some of the frequency bands of the single DSL channel and frequency bands of at least one other DSL channel to support the data communication when the loop length of the single DSL channel is unfavorable or the data rate of the data communication is unfavorable.
Abstract:
The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.
Abstract:
A power amplifier includes an input transistor, an input bias circuit, an output transistor, and a power down circuit. The input transistor includes a gate, a drain, and a source, wherein the source of the input transistor is coupled to a supply voltage return and the gate of the input transistor is operably coupled to receive an outbound radio frequency (RF) signal. The input bias circuit is operably coupled to provide an enabling bias voltage to the gate of the input transistor during transmit mode and to provide a disabling bias voltage to the gate of the input transistor during power down mode. The output transistor includes a gate, a drain, and a source, wherein the drain of the output transistor is coupled to provide an output of the power amplifier and the source of the output transistor is coupled to the drain of the input transistor. The power down circuit is operably coupled to provide an output enabling bias voltage to the gate of the output transistor during the transmit mode and to provide an output disabling bias voltage to the gate of the output transistor during the power down mode, wherein the output disabling bias voltage is of a value to distribute gate oxide stress between the input transistor and the output transistor.
Abstract:
A transformer balun is obtained that is symmetrical in structure, provides high current, or high voltage, amplification and has high coupling coefficients while maintaining minimal overall size. The balun structure includes primary and secondary metal windings at separate layer interfaces. The primary and secondary metal windings are symmetrical and can have any number of turns, which is only limited by integrated circuit area and capacitance. Accordingly, the, primary and secondary windings may be on as many layers as needed. Further, the primary and/or secondary may include a center tap ground, which enables the winding to be used as a differential port.