公开(公告)号：US20140006647A1

公开(公告)日：2014-01-02

申请号：US13928899

申请日：2013-06-27

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Nobuhiko Sugasawa ,  Yuta Kobayashi ,  Masataka Goto

IPC分类号： G06F13/34 ,  G06F3/06

CPC分类号： G06F13/34 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0688

摘要： There is provided a bridge device in which a reception unit receives first transfer information specifying a read address from an external device; a transfer information storage stores the first transfer information; a first processing unit generates a first command to instruct reading data from the read address of a data storage based on the first transfer information read from the transfer information storage and outputs the first command to the first controller; a data buffer retains the data read by the first controller from the read address; and a second processing unit generates a second command to instruct the second controller to read the data retained in the data buffer, and outputs the second command to the second controller.

摘要翻译： 提供一种桥接器件，其中接收单元从外部设备接收指定读取地址的第一传送信息; 传送信息存储器存储第一传送信息; 第一处理单元基于从传送信息存储读取的第一传送信息，生成指示从数据存储器的读取地址读取数据的第一命令，并将第一命令输出到第一控制器; 数据缓冲器将由第一控制器读取的数据从读取地址保存; 并且第二处理单元产生第二命令以指示第二控制器读取保留在数据缓冲器中的数据，并将第二命令输出到第二控制器。

公开(公告)号：US20130205105A1

公开(公告)日：2013-08-08

申请号：US13825027

申请日：2011-01-26

申请人： Masanori Nakata ,  Noriyuki Kushiro ,  Yoshiaki Ito

发明人： Masanori Nakata ,  Noriyuki Kushiro ,  Yoshiaki Ito

IPC分类号： G06F12/00

CPC分类号： G06F13/34 ,  G06F12/00 ,  G06F13/28 ,  G06F13/32

摘要： A DMA controller comprises a reading start address register storing a reading start address from which reading starts; a reading data size register storing the size of data to be read in a single reading operation; an offset value register storing an offset value for updating the reading start address after the reading operation ends; a repetition upper limit value register storing the upper limit value of the number of times of repetition of the reading operation; and a repetition counter register storing the number of times of repetition of the reading operation. The controller of the DMA controller outputs an interrupt signal indicating that the processing of the DMA controller ends when the value stored in the repetition counter register reaches the value stored in the repetition upper limit value register.

摘要翻译： DMA控制器包括读取开始地址寄存器，其存储从其开始读取的读取开始地址; 读取数据大小寄存器，存储在单次读取操作中要读取的数据的大小; 偏移值寄存器，用于在读取操作结束之后存储用于更新读取开始地址的偏移值; 存储读取操作的重复次数的上限值的重复上限值寄存器; 以及存储读取操作的重复次数的重复计数器寄存器。 当存储在重复计数器寄存器中的值达到存储在重复上限值寄存器中的值时，DMA控制器的控制器输出指示DMA控制器的处理结束的中断信号。

公开(公告)号：US07970959B2

公开(公告)日：2011-06-28

申请号：US11360609

申请日：2006-02-24

申请人： Kenichiro Kuroki ,  Kenji Sato

发明人： Kenichiro Kuroki ,  Kenji Sato

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G06F13/34 ,  Y02D10/14

摘要： A DMA transfer system includes a DMA controller having at least one channel coupled to a system bus, the DMA controller configured to perform a DMA transfer via the system bus according to a DMA transfer setting of the at least one channel, and a DMAC control unit coupled to the DMA controller, wherein the DMAC control unit includes a plurality of virtual channels configured to have respective DMA transfer settings made thereto, a virtual channel arbiter configured to select one of the plurality of virtual channels, and a DMA setting circuit configured to read a DMA transfer setting of the selected virtual channel to write the read DMA transfer setting to the at least one channel of the DMA controller.

摘要翻译： DMA传输系统包括具有耦合到系统总线的至少一个通道的DMA控制器，DMA控制器被配置为根据至少一个通道的DMA传输设置经由系统总线执行DMA传输，以及DMAC控制单元 耦合到所述DMA控制器，其中所述DMAC控制单元包括被配置为具有相应的DMA传输设置的多个虚拟通道，被配置为选择所述多个虚拟通道中的一个的虚拟通道仲裁器，以及被配置为读取的DMA设置电路 所选择的虚拟通道的DMA传输设置将读DMA传输设置写入DMA控制器的至少一个通道。

公开(公告)号：US5072365A

公开(公告)日：1991-12-10

申请号：US457647

申请日：1989-12-27

申请人： Bradley G. Burgess ,  James B. Eifert ,  John P. Dunn

发明人： Bradley G. Burgess ,  James B. Eifert ,  John P. Dunn

IPC分类号： G06F13/28 ,  G06F13/34

CPC分类号： G06F13/34

摘要： A data processing system having a direct memory access controller (DMAC) which can be interrupted with a prioritized signal to vary bus mastership of a communication bus in the system. A prioritized interrupt signal is sent to a CPU when the DMAC has bus mastership. The CPU only informs the DMAC of the highest priority cumulative interrupt priority. With the use of a mask value, the interrupt may be selectively screened by the DMAC so that selective interrupts may remove bus mastership from the DMAC.

公开(公告)号：US4837677A

公开(公告)日：1989-06-06

申请号：US744850

申请日：1985-06-14

申请人： Gilbert S. Burrus, Jr. ,  Ronald J. Cooper ,  Michael R. Marr ,  Mario A. Marsico ,  John C. Pescatore ,  Paul D. Sullivan

发明人： Gilbert S. Burrus, Jr. ,  Ronald J. Cooper ,  Michael R. Marr ,  Mario A. Marsico ,  John C. Pescatore ,  Paul D. Sullivan

IPC分类号： H04L29/04 ,  G06F13/00 ,  G06F13/12 ,  G06F13/34

CPC分类号： G06F13/34

摘要： Bus interconnection between the system busses of a multi-port communications controller and the busses of one or more multi-port adapters is facilitated with a new architecture for providing an interconnection controller. A programmably adjustable adapter and port interface controller is combined via a scannerless communications controller with a bus interconnection control logic that handles both DMA and interrupt mode data transfers for a large number of channels. The invention provides an improved apparatus and method for transferring data to or from numerous communication channel devices within a processor based communications system in such a manner that the optimum mode of data transfer may be individually programmed for each channel as system environment conditions demand.

摘要翻译： 用于提供互连控制器的新架构便于多端口通信控制器的系统总线与一个或多个多端口适配器的总线之间的总线互连。 可编程调节的适配器和端口接口控制器通过无扫描器通信控制器与总线互连控制逻辑组合，总线互连控制逻辑可处理大量通道的DMA和中断模式数据传输。 本发明提供了一种用于在基于处理器的通信系统内向多个通信信道设备传送数据或从多个通信信道设备传送数据的改进的设备和方法，使得可以根据系统环境条件要求为每个信道单独编程数据传输的最佳模式。

公开(公告)号：US4716523A

公开(公告)日：1987-12-29

申请号：US744852

申请日：1985-06-14

申请人： Gilbert S. Burrus, Jr. ,  Ronald J. Cooper ,  Michael R. Marr ,  John C. Pescatore ,  Mario A. Marsico

发明人： Gilbert S. Burrus, Jr. ,  Ronald J. Cooper ,  Michael R. Marr ,  John C. Pescatore ,  Mario A. Marsico

IPC分类号： H04L29/04 ,  G06F13/00 ,  G06F13/12 ,  G06F13/34 ,  G06F13/32

CPC分类号： G06F13/34

摘要： Both DMA access and character interrupt driven access modes of service are provided to multiple communication ports by an integrated arbitration DMA/interrupt controller utilizing its own resident randomly accessible memory. Pipelined logic control architecture for handling service mode adaptations for each individual port and for managing memory accesses to main system memory enables the use of the random access memory with its inherent time delays in a manner that virtually eliminates the effect of any time delay in overall memory access throughput.

摘要翻译： DMA访问和字符中断驱动的访问服务模式都通过集成的仲裁DMA /中断控制器提供给多个通信端口，该仲裁DMA /中断控制器利用其本身的随机可访问存储器。 用于处理每个单独端口的服务模式适配和用于管理对主系统存储器的存储器访问的流水线逻辑控制架构使得能够以其固有的时间延迟来使用随机存取存储器，其方式实际上消除了整个存储器中的任何时间延迟的影响 访问吞吐量。

公开(公告)号：US4490788A

公开(公告)日：1984-12-25

申请号：US427070

申请日：1982-09-29

申请人： Marvin W. Rasmussen

发明人： Marvin W. Rasmussen

IPC分类号： E21B47/00 ,  G06F13/34 ,  G06F13/40 ,  G06F3/00

CPC分类号： E21B47/00 ,  G06F13/34 ,  G06F13/4022

摘要： A well-logging well-site data acquisition and data processing system is disclosed. A central processing unit including a main memory and a single data bus is provided for data transfers with a first plurality of peripheral units. A plurality of serial link units are also provided. Each serial link unit includes a plurality of serial data input/output channels where each serial channel sends on transmit lines and receives on receive lines serial data between a second plurality of peripheral units connected to a serial link unit. A processor interface unit is provided for controlling the transfer of data between the host central processor unit and the plurality of serial link units. A microprocessor unit is provided as a communications controller for initiating the transfer of data between the plurality of serial link units and the processor interface unit. The plurality of serial link units in cooperation with the microprocessor unit and the processor interface unit enable the simultaneous input/output transfer of data to the peripherals to occur thereby increasing the effective data transfer rate of the system.

摘要翻译： 公开了一种测井井场数据采集和数据处理系统。 提供包括主存储器和单个数据总线的中央处理单元用于与第一多个外围单元的数据传输。 还提供了多个串行链路单元。 每个串行链路单元包括多个串行数据输入/输出通道，其中每个串行通道在发送线上发送，并且在连接到串行链路单元的第二多个外围单元之间的接收线上接收串行数据。 提供处理器接口单元，用于控制主机中央处理器单元和多个串行链路单元之间的数据传输。 提供微处理器单元作为通信控制器，用于启动多个串行链路单元和处理器接口单元之间的数据传输。 与微处理器单元和处理器接口单元协作的多个串行链路单元使得能够同时输入/输出向外围设备传送数据，从而增加系统的有效数据传输速率。

公开(公告)号：US4225942A

公开(公告)日：1980-09-30

申请号：US973364

申请日：1978-12-26

申请人： Frederick E. Kobs ,  Joseph L. Ryan ,  Minoru Inoshita ,  Gerald N. Winfrey

发明人： Frederick E. Kobs ,  Joseph L. Ryan ,  Minoru Inoshita ,  Gerald N. Winfrey

IPC分类号： G06F13/24 ,  G06F3/153 ,  G06F13/34 ,  G09G1/16 ,  G09G5/00 ,  G06F9/46

CPC分类号： G09G5/001 ,  G06F13/34 ,  G06F3/153 ,  G09G2360/18

摘要： A microprocessor controlled cathode ray tube display system has a plurality of peripheral devices all connected in common to a system bus. Apparatus in each peripheral device activates a single interrupt signal. A single acknowledge response signal to all the devices enables the interrupting device to place its address signals on the system bus thereby initiating a firmware routine for making the interrupting device operative with the system.

摘要翻译： 微处理器控制的阴极射线管显示系统具有多个共同连接到系统总线的外围设备。 每个外围设备中的设备激活单个中断信号。 对所有设备的单个确认响应信号使得中断设备能够将其地址信号放置在系统总线上，从而启动用于使中断设备与系统一起操作的固件程序。

公开(公告)号：US4090238A

公开(公告)日：1978-05-16

申请号：US729348

申请日：1976-10-04

申请人： Paul Michael Russo

发明人： Paul Michael Russo

IPC分类号： G06F9/48 ,  G06F13/32 ,  G06F13/34 ,  G06F9/18 ,  G06F13/00

CPC分类号： G06F9/4812 ,  G06F13/34

摘要： Circuit for receiving service request signals from peripheral devices in a computer system and providing an address to the computer to effect a program transfer to an appropriate service subroutine. An interrupt request signal is generated to cause the computer to jump to a subroutine. A DMA (direct memory access) request is used to store the address at which the proper subroutine is stored. The proper subroutine depends on the highest priority device supplying a service request signal and on the status of that device. Provision is also made for storing a double-length address.

摘要翻译： 用于从计算机系统中的外围设备接收服务请求信号的电路，并向计算机提供地址以实现程序传送到适当的服务子程序。 产生中断请求信号，使计算机跳转到子程序。 DMA（直接存储器访问）请求用于存储存储正确子程序的地址。 正确的子程序取决于提供服务请求信号的最高优先级设备和该设备的状态。 还提供了存储双长度地址的规定。

公开(公告)号：US4050058A

公开(公告)日：1977-09-20

申请号：US625627

申请日：1975-10-24

申请人： Richard A. Garlic

发明人： Richard A. Garlic

IPC分类号： G06F9/22 ,  G06F13/34 ,  G06F15/16 ,  G06F15/78 ,  G06F3/00

CPC分类号： G06F9/22 ,  G06F13/34 ,  G06F15/16 ,  G06F15/7864

摘要： A highly parallel microprocessor using a logic gating structure and a microinstruction organization which permits direct access by each of the microprocessor components to a tri-bus system. Operation is defined by a single phase clock, during which all portions of a microinstruction are executed. The system further permits overlap operation for microprocessor instructions, thereby allowing for the fetching of a next instruction while executing a current instruction. The use of general purpose, non-dedicated registers is contemplated, thereby to avoid the need for multi-phase clocking.

摘要翻译： 使用逻辑门控结构和微指令组织的高度并行微处理器，其允许每个微处理器组件直接访问三总线系统。 操作由单相时钟定义，在此期间执行微指令的所有部分。 该系统进一步允许微处理器指令的重叠操作，从而允许在执行当前指令时取出下一条指令。 考虑使用通用非专用寄存器，从而避免了对多相时钟的需要。