公开(公告)号：US08069428B1

公开(公告)日：2011-11-29

申请号：US11818005

申请日：2007-06-12

Applicant: Kenneth Y. Ogami ,  Doug Anderson ,  Matthew Pleis ,  Frederick Redding Hood, III

Inventor： Kenneth Y. Ogami ,  Doug Anderson ,  Matthew Pleis ,  Frederick Redding Hood, III

IPC: G06F17/50

CPC classification number: G06F8/34 ,  G06F9/22 ,  G06F9/44505 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5054

Abstract: A method and apparatus for configuring a microcontroller. An XML description of the microcontroller's hardware resources may be accessed. A user may select from available hardware resources and pre-defined user modules to select a configuration. Configuration information, which may include register bit patterns and microprocessor instructions, may be automatically generated. Additionally, application programming interface calls and structure, as well as interrupt vector tables may be automatically generated. Embodiments of the present invention provide improved ease of use and the ability to manage greater complexity in the configuration of configurable microcontrollers.

Abstract translation: 一种用于配置微控制器的方法和装置。 可以访问微控制器的硬件资源的XML描述。 用户可以从可用的硬件资源和预定义的用户模块中进行选择以选择配置。 可以自动生成包括寄存器位模式和微处理器指令的配置信息。 另外，应用编程接口调用和结构以及中断向量表可能会自动生成。 本发明的实施例提供改进的易用性和管理可配置微控制器的配置的更大复杂性的能力。

公开(公告)号：US20110099356A1

公开(公告)日：2011-04-28

申请号：US12912093

申请日：2010-10-26

Applicant: Ernest SCHAEFER

Inventor： Ernest SCHAEFER

IPC: G06F9/302

CPC classification number: G01R33/3852 ,  G01R33/385 ,  G06F9/22 ,  G06F9/3001 ,  G06F9/30014

Abstract: A device for real-time correction of set-point signals intended to receive at the input set-point signals and to deliver at its output set-point signals that are modified to compensate for defects, negative effects or the like subsequently encountered during the processing and/or the application of the set-point signals. This device (1) includes at least one circuit (1′) that is based on a microprogrammed structure and composed of several subassemblies (3, 4, 5, 6, 6′) that work with digital components essentially including a micro-sequencer (3) forming a counter, a memory (4) for storing micro-instructions, and a processing unit (5) combined with at least one working memory (6, 6′) and integrating arithmetic calculation modules (7, 7′), whereby the processing unit (5) modifies the data of set-point signals in accordance with the micro-instructions that are addressed by the micro-sequencer (3) and by taking into account the correction coefficients that are provided.

Abstract translation: 用于实时校正设定点信号的设备，用于在输入设定点处接收信号并在其输出设定点处传送被修改以补偿在处理期间随后遇到的缺陷，负面影响等的信号 和/或设置点信号的应用。 该装置（1）包括至少一个基于微程序结构并由几个子组件（3,4,5,6,6'）构成的电路（1'），该组件与基本上包括微定序器的数字组件 3）形成计数器，用于存储微指令的存储器（4），以及与至少一个工作存储器（6,6'）组合的积分算术计算模块（7,7'）的处理单元（5），由此 处理单元（5）根据由微定序器（3）寻址的微指令并考虑所提供的校正系数来修改设定点信号的数据。

公开(公告)号：US20100174889A1

公开(公告)日：2010-07-08

申请号：US12349307

申请日：2009-01-06

Applicant: Richard L. Maliszewski ,  James P. Held ,  Daniel Baumberger

Inventor： Richard L. Maliszewski ,  James P. Held ,  Daniel Baumberger

IPC: G06F9/455 ,  G06F9/30

CPC classification number: G06F9/45533 ,  G06F9/22 ,  G06F9/30174 ,  G06F9/30189

Abstract: Embodiments of apparatuses, methods, and systems for modifying the behavior of a guest installed to run within a VM are disclosed. In one embodiment, an apparatus includes virtualization logic, first storage, second storage, decode logic, and multiplexing logic. The virtualization logic is to provide a mode in which to operate a virtual machine. The first storage is to store a first plurality of micro-instructions to control the apparatus. The second storage is to store a second plurality of micro-instructions to control the apparatus. The decode logic is to decode a macro-instruction into one of a first plurality and a second plurality of micro-instructions. The multiplexing logic is to cause the macro-instruction to be decoded into the second plurality of micro-instructions instead of the first plurality of micro-instructions only when issued from the virtual machine.

Abstract translation: 公开了用于修改安装在VM内运行的客户端的行为的装置，方法和系统的实施例。 在一个实施例中，设备包括虚拟化逻辑，第一存储，第二存储，解码逻辑和多路复用逻辑。 虚拟化逻辑是提供一种操作虚拟机的模式。 第一存储器是存储第一多个微指令以控制该装置。 第二存储器是存储第二多个微指令以控制该装置。 解码逻辑是将宏指令解码为第一多个和第二多个微指令之一。 复用逻辑是仅在从虚拟机发出时，使宏指令被解码成第二多个微指令而不是第一多个微指令。

公开(公告)号：US5053989A

公开(公告)日：1991-10-01

申请号：US089558

申请日：1987-08-26

Applicant: Yasuo Masaki

Inventor： Yasuo Masaki

IPC: G06F9/22

CPC classification number: G06F9/22

Abstract: A microprogram loaded in a microprogram memory by a host CPU is read out by a microprogram read control circuit in a vacant period existing in each cycle of operation of a hardware unit, whereby the microprogram is transmitted to each circuit of the hardware unit through a microprogram read-only bus. Each circuit of the hardware unit comprises a decoder and operation thereof is controlled based on a microinstruction decoded by the decoder.

Abstract translation: 由主机CPU装载在微程序存储器中的微程序由硬件单元的每个操作周期中存在的空闲周期中的微程序读取控制电路读出，由此微程序通过微程序传送到硬件单元的每个电路 只读总线 硬件单元的每个电路包括解码器，并且其操作基于由解码器解码的微指令来控制。

公开(公告)号：US5053941A

公开(公告)日：1991-10-01

申请号：US464713

申请日：1990-01-12

Applicant: Susan E. Carrie

Inventor： Susan E. Carrie

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/38

CPC classification number: G06F9/22 ,  G06F9/268 ,  G06F9/3869

Abstract: An asynchronous micro-machine/interface responsive to a central processing unit (CPU) in which the CPU and the micro-machine/interface are run on clocks which are asynchronous from one another is provided. The inventive asynchronous micro-machine/interface has data path elements for receiving an incoming instruction and for performing actions requested by the incoming instruction, as well as a means for synchronizing the incoming instruction to the clock of the micro-machine/interface and for performing actions within the data path elements prior to the execution of the incoming instruction and during transfer of control, by the micro-machine/interface, to the routine that is associated with the incoming instruction.

Abstract translation: 提供了响应中央处理单元（CPU）的异步微机/接口，其中CPU和微机/接口在彼此异步的时钟上运行。 本发明的异步微机/接口具有用于接收输入指令并用于执行由输入指令请求的动作的数据路径元件，以及用于将输入指令与微机/接口的时钟同步并用于执行 在执行输入指令之前和在由微机/接口传送控制期间到数据路径元素内的动作到与输入指令相关联的例程。

公开(公告)号：US4050058A

公开(公告)日：1977-09-20

申请号：US625627

申请日：1975-10-24

Applicant: Richard A. Garlic

Inventor： Richard A. Garlic

IPC: G06F9/22 ,  G06F13/34 ,  G06F15/16 ,  G06F15/78 ,  G06F3/00

CPC classification number: G06F9/22 ,  G06F13/34 ,  G06F15/16 ,  G06F15/7864

Abstract: A highly parallel microprocessor using a logic gating structure and a microinstruction organization which permits direct access by each of the microprocessor components to a tri-bus system. Operation is defined by a single phase clock, during which all portions of a microinstruction are executed. The system further permits overlap operation for microprocessor instructions, thereby allowing for the fetching of a next instruction while executing a current instruction. The use of general purpose, non-dedicated registers is contemplated, thereby to avoid the need for multi-phase clocking.

Abstract translation: 使用逻辑门控结构和微指令组织的高度并行微处理器，其允许每个微处理器组件直接访问三总线系统。 操作由单相时钟定义，在此期间执行微指令的所有部分。 该系统进一步允许微处理器指令的重叠操作，从而允许在执行当前指令时取出下一条指令。 考虑使用通用非专用寄存器，从而避免了对多相时钟的需要。

公开(公告)号：US4034345A

公开(公告)日：1977-07-05

申请号：US606162

申请日：1975-08-20

Applicant: August Deis

Inventor： August Deis

IPC: G06F9/22 ,  G06F9/32 ,  G06F9/00

CPC classification number: G06F9/226 ,  G06F9/22

Abstract: The invention relates to a microprogrammed computer whose architecture is determined by a simple and rigid format of the controlling micro-instruction. Each micro-instruction controls a data transfer and has at least four parts each of which are within a single micro-instruction. A first part always specifies the data source and data sink between which the data transfer is to take place. In a second part, conditions are stated for transfer to, or writing into the data sink. In a third part, a specific counting register out of a number of counting registers is addressed and, furthermore, it is specified how the contents of the counting register must be modified parallel to the transfer. In a fourth part, further data is contained; the fourth part may be controlled as a data source, with data transfer from the source to an arbitrary data sink being possible. In the case of transfer to the operation register of the arithmetic unit, such data indicates the logic or arithmetic operation. In the case of transfer to, for example, a counting register, the data may be employed to derive an initial address therefrom. The operation code register may advantageously have a capacity which corresponds to the length of two storage words.

Abstract translation: 本发明涉及一种微程序计算机，其架构由控制微指令的简单且刚性的格式确定。 每个微指令控制数据传输，并且至少有四个部分，每个微处理器都在单个微指令内。 第一部分总是指定要进行数据传输的数据源和数据宿。 在第二部分中，规定了转移到数据接收器或写入数据接收器的条件。 在第三部分中，寻址多个计数寄存器中的特定计数寄存器，此外，还规定了计数寄存器的内容必须如何与传输并行进行修改。 第四部分包含进一步的数据; 可以将第四部分作为数据源进行控制，从源到数据接收器的数据传输是可能的。 在传送到运算单元的运算寄存器的情况下，这些数据表示逻辑运算或算术运算。 在转移到例如计数寄存器的情况下，可以使用数据来从其导出初始地址。 操作码寄存器有利地具有对应于两个存储字长度的容量。

公开(公告)号：US3638184A

公开(公告)日：1972-01-25

申请号：US3638184D

申请日：1970-06-08

Applicant: BELL TELEPHONE LABOR INC

Inventor： BEUSCHER HUGH JACOB ,  NELSON DONALD ROBERT ,  SISSON WILLIAM HOWARD ,  TOY WING NOON

IPC: G06F9/22 ,  G06F11/16 ,  H03K13/32

CPC classification number: G06F9/22 ,  G06F11/085

Abstract: A conventional decoder of the type that converts an m-out-of-n representation to activation of only a single one of plural output lines is modified to have powerful self-checking capabilities. The modified decoder is adapted to be included in a control system in which the words stored in a microprogram memory are coded in an m-out-of-n format. Such a system automatically detects the occurrence of any no-output or multiple-output readout from the memory.

Abstract translation: 将m-out-of-n表示转换为仅激活多个输出行中的单个输入行的类型的常规解码器被修改为具有强大的自检功能。 修改后的解码器适于包含在控制系统中，其中存储在微程序存储器中的字以m-out-n格式编码。 这样的系统自动检测从存储器发出的任何无输出或多输出读出。

公开(公告)号：US20240168832A1

公开(公告)日：2024-05-23

申请号：US18425152

申请日：2024-01-29

Applicant: NCR Voyix Corporation

Inventor： Alexander Arrabis Bronola

IPC: G06F9/54 ,  G06F9/22 ,  G06F9/445 ,  G06Q20/10 ,  G06Q20/18 ,  G06Q20/20

CPC classification number: G06F9/544 ,  G06F9/22 ,  G06F9/44526 ,  G06F9/546 ,  G06Q20/1085 ,  G06Q20/18 ,  G06Q20/20

Abstract: Inter-microservice communications are managed through in-memory connection routing. A sending microservice writes a message over a port associated with the connection. The message is routed directly to one or more receiving microservices associated with the connection over their ports associated with the connection. The message may be converted to a different format or multiple different formats through plugins processed when the message is received over the sending microservice's port and before the converting messages are routed over the receiving microservices' ports. The inter-microservice communications are hardware and platform independent or agnostic, such that the microservices associated with the connection can be processed on different hardware and different platforms from one another.

公开(公告)号：US20230273811A1

公开(公告)日：2023-08-31

申请号：US17682091

申请日：2022-02-28

Applicant: Intel Corporation

Inventor： Michael Mishaeli ,  Eyal Oz-Sinay ,  Gavri Berger ,  Gal Ofir ,  Tomer Weiner ,  Arkady Bramnik

IPC: G06F9/48 ,  G06F9/22

CPC classification number: G06F9/4843 ,  G06F9/22

Abstract: In one embodiment, an apparatus includes: an instruction fetch circuit to fetch instructions; a decode circuit coupled to the instruction fetch circuit to decode the fetched instructions into micro-operations (pops); a scheduler coupled to the decode circuit to schedule the pops for execution; and an execution circuit coupled to the scheduler, the execution circuit comprising a plurality of execution ports to execute the pops. The scheduler may be configured to: schedule at least some pops of a first type for redundant execution on symmetric execution ports of the plurality of execution ports; and schedule pops of a second type for non-redundant execution on a single execution port of the plurality of execution ports. Other embodiments are described and claimed.