公开(公告)号：US06515316B1

公开(公告)日：2003-02-04

申请号：US09616852

申请日：2000-07-14

申请人： Michael Wojtowicz ,  Tsung-Pei Chin ,  Michael E. Barsky ,  Ronald W. Grundbacher

发明人： Michael Wojtowicz ,  Tsung-Pei Chin ,  Michael E. Barsky ,  Ronald W. Grundbacher

IPC分类号： H01L29778

CPC分类号： H01L29/7782 ,  H01L29/2003

摘要： A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.

摘要翻译： HEMT器件包括设置在衬底上的缓冲层。 部分松弛的通道设置在缓冲层之上，阻挡层设置在通道上。 盖层设置在阻挡层之上并且栅极位于阻挡层上。 源极和漏极位于栅极的相对侧上的势垒层上。

公开(公告)号：US20020105015A1

公开(公告)日：2002-08-08

申请号：US10115983

申请日：2002-04-05

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Minoru Kubo ,  Katsuya Nozawa ,  Masakatsu Suzuki ,  Takeshi Uenoyama ,  Yasuhito Kumabuchi

IPC分类号： H01L029/80

CPC分类号： H01L29/66431 ,  H01L21/8238 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1029 ,  H01L29/161 ,  H01L29/7782

摘要： Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.

摘要翻译： Si和SiGeC层形成在Si衬底上的NMOS晶体管中。 使用存在于SiGeC和Si层之间的异质界面处的导带的不连续部分来形成载流子积累层。 电子在作为通道的载流子累积层中行进。 在SiGeC层中，电子迁移率大于硅中的电子迁移率，从而增加NMOS晶体管的工作速度。 在PMOS晶体管中，通过在SiGe和Si层之间的界面处使用价带的不连续部分来形成空穴行进的沟道。 SiGe层中的空穴迁移率也大于Si层，因此增加PMOS晶体管的工作速度。 可以提供具有场效应晶体管的半导体器件，其具有在晶体缺陷中减少的沟道。

公开(公告)号：US20020079507A1

公开(公告)日：2002-06-27

申请号：US09927939

申请日：2001-08-13

发明人： Kyu Hwan Shim ,  Hong Seung Kim ,  Seung Yun Lee ,  Jin Yeoung Kang

IPC分类号： H01L031/0328

CPC分类号： H01L29/66431 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7782

摘要： There is disclosed a method for fabricating a SiGe MODFET device using a metal oxide film. The present invention provides a SiGe MODFET device with improved operation speed and reduced non-linear operation characteristic caused in a single channel stricture devices, by increasing the mobility of the carriers in the SiGe MODEFT having a metal-oxide gate, and method of fabricating the same. In order to accomplish the above object, the present invention grows a silicon buffer layer and a SiGe buffer layer on a silicon substrate by low-temperature process, so that defects caused by the mismatch of the lattice constants being applied to the epitaxial layer from the silicon substrate are constrained in the buffer layered formed by the low-temperature process.

摘要翻译： 公开了使用金属氧化物膜制造SiGe MODFET器件的方法。 本发明通过增加具有金属氧化物栅的SiGe MODEFT中的载流子的迁移率，提供了在单通道限制器件中引起的具有改善的操作速度和减小的非线性操作特性的SiGe MODFET器件，以及制造 相同。 为了实现上述目的，本发明通过低温处理在硅衬底上生长硅缓冲层和SiGe缓冲层，使得由晶格常数不匹配引起的缺陷从外延层施加到外延层 硅衬底被限制在由低温工艺形成的缓冲层中。

公开(公告)号：US06399970B2

公开(公告)日：2002-06-04

申请号：US08931562

申请日：1997-09-16

申请人： Minoru Kubo ,  Katsuya Nozawa ,  Masakatsu Suzuki ,  Takeshi Uenoyama ,  Yasuhito Kumabuchi

发明人： Minoru Kubo ,  Katsuya Nozawa ,  Masakatsu Suzuki ,  Takeshi Uenoyama ,  Yasuhito Kumabuchi

IPC分类号： H01L29778

CPC分类号： H01L29/66431 ,  H01L21/8238 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1029 ,  H01L29/161 ,  H01L29/7782

摘要： Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.

摘要翻译： Si和SiGeC层形成在Si衬底上的NMOS晶体管中。 使用存在于SiGeC和Si层之间的异质界面处的导带的不连续部分来形成载流子积累层。 电子在作为通道的载流子累积层中行进。 在SiGeC层中，电子迁移率大于硅中的电子迁移率，从而增加NMOS晶体管的工作速度。 在PMOS晶体管中，通过在SiGe和Si层之间的界面处使用价带的不连续部分来形成空穴行进的沟道。 SiGe层中的空穴迁移率也大于Si层，因此增加PMOS晶体管的工作速度。 可以提供具有场效应晶体管的半导体器件，其具有在晶体缺陷中减少的沟道。

公开(公告)号：US4994866A

公开(公告)日：1991-02-19

申请号：US293527

申请日：1989-01-05

申请人： Yuji Awano

发明人： Yuji Awano

IPC分类号： H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165 ,  H01L29/778 ,  H01L29/80

CPC分类号： H01L29/165 ,  H01L21/823807 ,  H01L27/0605 ,  H01L29/1054 ,  H01L29/7782 ,  H01L29/802 ,  H01L27/092

摘要： A complementary semiconductor device (CMOS gate) including a p-channel transistor (PMOS FET) and an n-channel transistor (NMOS FET). A silicon substrate, a channel layer for the p-channel transistor which comprises a first Si.sub.1-x Ge.sub.x layer, a Ge layer, and a second Si.sub.1-x Ge.sub.x layer are formed in sequence on the silicon substrate. A silicon layer, as another channel layer for the n-channel transistor, is formed on the channel layer. The ratio "x" of the first Si.sub.1-x Ge.sub.x layer is continuously increased from 0 to 1, and the ratio "x" of the second Si.sub.1-x Ge.sub.x layer is continuously decreased from 1 to 0.

公开(公告)号：US20190067431A1

公开(公告)日：2019-02-28

申请号：US16107058

申请日：2018-08-21

申请人： Vanguard International Semiconductor Corporation

发明人： Hsin-Chih LIN ,  Shin-Cheng LIN ,  Yung-Hao LIN

IPC分类号： H01L29/423 ,  H01L21/265 ,  H01L29/778 ,  H01L29/66

CPC分类号： H01L29/4236 ,  H01L21/26546 ,  H01L29/2003 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7782 ,  H01L29/7783 ,  H01L29/7784 ,  H01L29/7785 ,  H01L29/7786 ,  H01L29/7787

摘要： A HEMT device is provided. The HEMT device includes a substrate, a first epitaxial layer, a second epitaxial layer, an insulating layer, a gate, a source, and a drain. The first epitaxial layer is formed on the substrate. The second epitaxial layer is formed on the first epitaxial layer. The insulating layer is formed on the second epitaxial layer. The gate is formed in the insulating layer and extends into the second epitaxial layer. The source and the drain are formed in the insulating layer and extend into the second epitaxial layer, wherein the source and the drain are located on both sides of the gate.

公开(公告)号：US20180308926A1

公开(公告)日：2018-10-25

申请号：US15960845

申请日：2018-04-24

申请人： Murata Manufacturing Co., Ltd.

发明人： Shinnosuke TAKAHASHI ,  Masayuki AOIKE

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/778 ,  H01L29/423 ,  H01L29/40

CPC分类号： H01L29/0619 ,  H01L21/76 ,  H01L21/76224 ,  H01L29/0626 ,  H01L29/1075 ,  H01L29/1083 ,  H01L29/205 ,  H01L29/405 ,  H01L29/42312 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7783 ,  H01L29/7786

摘要： A semiconductor layer arranged on a semiconductor substrate includes an active region and an element isolation region that surrounds the first active region when viewed in plan. A field effect transistor is formed in the active region. A plurality of guard ring electrodes separated from each other affect a potential of the active region through the element isolation region. An interlayer insulating film is formed over the semiconductor layer, the field effect transistor, and the guard ring electrodes. At least one guard ring connection wiring formed on the interlayer insulating film electrically interconnects the plurality of guard ring electrodes.

公开(公告)号：US10079297B2

公开(公告)日：2018-09-18

申请号：US15452999

申请日：2017-03-08

申请人： FUJITSU LIMITED

发明人： Akira Endoh

IPC分类号： H01L29/06 ,  H01L29/165 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

CPC分类号： H01L29/7786 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/165 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/7782 ,  H01L29/7784

摘要： A compound semiconductor device includes a compound semiconductor layer, a gate electrode disposed above the compound semiconductor layer, and source and drain electrodes disposed above the compound semiconductor layer with the gate electrode between the source and drain electrodes, wherein the compound semiconductor layer has a groove in a surface thereof at least between the source electrode and the gate electrode in a region between the source electrode and the drain electrode, the groove gradually deepened toward the source electrode.

公开(公告)号：US10020322B2

公开(公告)日：2018-07-10

申请号：US15390894

申请日：2016-12-27

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Daigo Ito ,  Takahisa Ishiyama ,  Katsuaki Tochibayashi ,  Yoshinori Ando ,  Yasutaka Suzuki ,  Mitsuhiro Ichijo ,  Toshiya Endo ,  Shunpei Yamazaki

IPC分类号： H01L29/10 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L29/778 ,  H01L29/24

CPC分类号： H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7786 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2224/05 ,  H01L2224/48463

摘要： A highly reliable semiconductor device which includes an oxide semiconductor is provided. Alternatively, a transistor having normally-off characteristics which includes an oxide semiconductor is provided. The transistor includes a first conductor, a first insulator, a second insulator, a third insulator, a first oxide, an oxide semiconductor, a second conductor, a second oxide, a fourth insulator, a third conductor, a fourth conductor, a fifth insulator, and a sixth insulator. The second conductor is separated from the sixth insulator by the second oxide. The third conductor and the fourth conductor are separated from the sixth insulator by the fifth insulator. The second oxide has a function of suppressing permeation of oxygen as long as oxygen contained in the sixth insulator is sufficiently supplied to the oxide semiconductor through the second oxide. The fifth insulator has a barrier property against oxygen.

公开(公告)号：US09971680B2

公开(公告)日：2018-05-15

申请号：US14731940

申请日：2015-06-05

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Wataru Uesugi ,  Tomoaki Atsumi ,  Naoaki Tsutsui ,  Hikaru Tamura ,  Takahiko Ishizu ,  Takuro Ohmaru

IPC分类号： G06F12/00 ,  G11C5/00 ,  H01L27/12 ,  H01L29/778 ,  H01L27/06 ,  H01L27/1156 ,  H01L29/24

CPC分类号： G06F12/00 ,  G11C5/00 ,  H01L27/0688 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7782

摘要： A semiconductor device including a register controller and a processor which includes a register is provided. The register includes a first circuit and a second circuit which includes a plurality of memory portions. The first circuit and the plurality of memory portions can store data by an arithmetic process of the processor. Which of the plurality of memory portions the data is stored in depends on a routine by which the data is processed. The register controller switches the routine in response to an interrupt signal. The register controller can make any one of the plurality of memory portions which corresponds to the routine store the data in the first circuit every time the routine is switched. The register controller can make data stored in any one of the plurality of memory portions which corresponds to the routine be stored in the first circuit every time the routine is switched.