公开(公告)号：US09966969B1

公开(公告)日：2018-05-08

申请号：US15490762

申请日：2017-04-18

Applicant: Analog Devices, Inc.

Inventor： Gil Engel ,  Shawn S. Kuo ,  Steven C. Rose

IPC: H03M1/66 ,  H03M1/12

CPC classification number: H03M1/662 ,  H03M1/0673 ,  H03M1/1215 ,  H03M1/66

Abstract: A time-interleaved digital-to-analog converter (DAC) uses M DAC cores to convert a digital input signal whose digital input words are spread to different DAC cores to produce a final analog outputs. The M DAC cores, operating in a time-interleaved fashion, can increase the sampling rate several times compared to the sampling rate of just one DAC. However, sequential time-interleaving DAC cores often exhibit undesirable spurs at the output. To spread those spurs to the noise floor, the time-interleaving DAC cores can be selected at a pseudo randomized manner or in a specific manner which can break up the sequential or periodic manner of selecting the DAC cores.

公开(公告)号：US20180102785A1

公开(公告)日：2018-04-12

申请号：US15816197

申请日：2017-11-17

Applicant: Innoaxis Co., Ltd

Inventor： Hwi-Cheol KIM

IPC: H03M1/66 ,  G09G3/20 ,  H03M7/30 ,  H03M1/74 ,  H03M1/78 ,  H03M1/00

CPC classification number: H03M1/66 ,  G09G3/2007 ,  G09G2310/027 ,  G09G2320/0276 ,  H03M1/00 ,  H03M1/747 ,  H03M1/76 ,  H03M1/785 ,  H03M7/30

Abstract: A digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end; a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; and a decoder configured to control the plurality of pass transistors. The plurality of the pass transistors are included in any one among a plurality of groups according to values of the gradation voltages, and the pass transistors included in the any one group are divided into a first group and a second group according to output gradation voltages, and pass transistors included in the first group and pass transistors included in the second group are different types of pass transistors.

公开(公告)号：US20180091203A1

公开(公告)日：2018-03-29

申请号：US15603621

申请日：2017-05-24

Applicant: Rohde & Schwarz GmbH & Co. KG

Inventor： Wolfgang Kufer

IPC: H04B7/06 ,  H03M1/66 ,  H01Q3/38 ,  G01S7/42

CPC classification number: H04B7/0617 ,  G01S7/42 ,  G06F1/10 ,  H01Q3/38 ,  H03M1/0624 ,  H03M1/66

Abstract: The invention relates to a method for controlling digital-to-analogue converters (DAC), the method comprising: providing a plurality of digital-to-analogue converters (DAC) of a multi-channel converter array wherein each DAC includes a separate clock generator; generating, by each clock generator, a RF carrier signal; converting, by each DAC, digital data signals into analogue RF data signals based on the carrier signals of the corresponding clock generators; providing a separate control signal for each clock generator wherein the control signals comprise control information such that when the control signals are applied to the corresponding clock generators the different analogue RF data signals provided at respective output terminals of each DAC comprise a pre-defined phase shift to each other; controlling the clock generator of each DAC directly and independently based on the provided control signals. The invention further relates to a converter arrangement RF transmit circuit arrangement.

公开(公告)号：US20180081386A1

公开(公告)日：2018-03-22

申请号：US15272136

申请日：2016-09-21

Applicant: Infineon Technologies Austria AG

Inventor： Dieter Draxelmayr

IPC: G05F3/26 ,  H03M1/66

CPC classification number: G05F3/267 ,  H03M1/66 ,  H03M1/742

Abstract: This disclosure describes a precise, fast, and relatively low power current-source for use in various applications, which may include driving power semiconductors such power MOSFETs and IGBTs. The current-source may provide both a constant current and a current profile over time which may charge and discharge the steering terminal (e.g. the gate) of a power semiconductor for precise control of switch timing. The current-source uses current steering digital-to-analog converter (DAC) technology and current mirrors to generate a high output current that is significantly immune to power supply and ground variability.

公开(公告)号：US20180071514A1

公开(公告)日：2018-03-15

申请号：US15696048

申请日：2017-09-05

Applicant: Boston Scientific Neuromodulation Corporation

Inventor： David Michael Wagenbach ,  Philip Leonard Weiss ,  Goran N. Marnfeldt ,  Kiran K. Gururaj ,  Pujitha Weerakoon

IPC: A61N1/02 ,  A61N1/05 ,  A61N1/372

CPC classification number: A61N1/025 ,  A61B5/04001 ,  A61N1/05 ,  A61N1/3605 ,  A61N1/36071 ,  A61N1/36125 ,  A61N1/37223 ,  H03M1/66

Abstract: Improved circuitry for measuring analog values in an implantable pulse generator is disclosed. The measurement circuitry executes instructions that define the timing and parameters of measurements to be taken. The instructions include instructions that are responsive to different types of triggers issued by different pulse definition circuits, which pulse definition circuits generate different stimulation waveforms at different groups of electrodes. The measurement circuitry is configurable to update the groups of electrodes used to deliver stimulation.

公开(公告)号：US09900021B1

公开(公告)日：2018-02-20

申请号：US15098292

申请日：2016-04-13

Applicant: HRL Laboratories, LLC

Inventor： Kenneth R. Elliott

IPC: H03M1/00 ,  H03M1/66 ,  G02F7/00 ,  G02F1/01

CPC classification number: H03M1/66 ,  G02F1/011 ,  G02F1/0121 ,  G02F7/00 ,  G02F2201/16 ,  H04B10/5051 ,  H04B10/516

Abstract: An apparatus comprised of a cascaded series of optical modulators addressed by a multi-bit digital word with each optical modulator in the cascaded series being responsive to a single bit in the multi-bit digital word and wherein each of the optical modulators in the cascaded series of optical modulators doubling in effective optical length as a bit index of the bit of the multi-bit digital word to which it is responsive increases by a bit index value equal to one. The apparatus may be used with a prior art analog optical modulator and an associated ADC, having a fixed bit width, to extend the number of bits beyond the fixed bit width that the ADC and analog optical modulator prior art combination can otherwise operate.

公开(公告)号：US09900016B1

公开(公告)日：2018-02-20

申请号：US15588065

申请日：2017-05-05

Applicant: INTEL IP CORPORATION

Inventor： Stefan Trampitsch ,  Daniel Gruber

IPC: H03M1/06 ,  H03M1/66

CPC classification number: H03M1/0602 ,  H03M1/0845 ,  H03M1/66

Abstract: An apparatus for compensating for nonlinearities in a DAC caused by variabilities of a power supply. The apparatus may include a power supply, a processing component, and a front-end circuit. The power supply may generate power, where the power includes variabilities in a power. The processing component may generate a digital signal. The front-end circuit may be operatively coupled to the power supply and the processing component. The front-end circuit may receive the power from the power supply, identify the nonlinearities in the power, receive the digital signal from the processing component, and adjust the digital signal for the nonlinearities to obtain an input signal to send to a digital to analog converter (DAC).

公开(公告)号：US09897976B2

公开(公告)日：2018-02-20

申请号：US15479499

申请日：2017-04-05

Applicant: Integrated Device Technology, Inc.

Inventor： Song Gao ,  Brian Buell ,  Katherine T. Blinick

IPC: H03M1/10 ,  G04F10/00 ,  H03M1/66

CPC classification number: G04F10/005 ,  G04G3/02 ,  G06F1/08 ,  H03M1/10 ,  H03M1/1009 ,  H03M1/66 ,  H03M1/82

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a plurality of capacitances. A number of the capacitances engaged may be selected to reduce jitter on the output clock signal. The capacitances may be used each cycle to calibrate the output clock signal.

公开(公告)号：US20180048338A1

公开(公告)日：2018-02-15

申请号：US15555939

申请日：2015-03-06

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wei Chen

IPC: H04B1/04 ,  H03M1/66

CPC classification number: H04B1/04 ,  H03M1/66 ,  H04B3/54 ,  H04B3/56 ,  H04B2203/5408 ,  H04B2203/5454

Abstract: Embodiments of the present invention disclose a power line communications device, and the power line communications device includes a USB interface, a protocol conversion module, a signal conversion module, a coupler, and a power line interface. A first end of the USB interface is connected to a first end of the protocol conversion module, a second end of the protocol conversion module is connected to a first end of the signal conversion module, a second end of the signal conversion module is connected to a first end of the coupler, and a second end of the coupler is connected to a first end of the power line interface. During implementation of the embodiments of the present invention, the USB interface may be used to provide a network signal for a terminal device.

公开(公告)号：US09857823B2

公开(公告)日：2018-01-02

申请号：US15081880

申请日：2016-03-26

Applicant: IXYS Corporation

Inventor： Eric Blom ,  Anatoliy Tsyrganovich ,  James Anderson

IPC: H01L35/00 ,  H01L37/00 ,  H03K3/42 ,  H03K17/78 ,  G05F3/16 ,  G05F3/04 ,  H03M1/10 ,  G05F1/46 ,  H03M1/66

CPC classification number: G05F3/16 ,  G05F1/461 ,  G05F3/04 ,  H03M1/1047 ,  H03M1/66

Abstract: A programmable temperature compensated voltage reference is disclosed. In an exemplary embodiment, an apparatus includes a digital-to-analog converter (DAC) that uses a reference voltage and a code to generate a DAC output voltage. The apparatus also includes a temperature compensator that uses a temperature measurement (T) and the DAC code to generate a temperature compensation signal. The temperature compensation signal is represented by a third order polynomial equation. The apparatus also includes a signal combiner that combines the DAC output voltage and the temperature compensation signal to generate a temperature compensated programmable reference voltage.