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公开(公告)号：US20240146310A1
公开(公告)日：2024-05-02
申请号：US18548044
申请日：2021-12-31
Applicant: ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.
Abstract: Provided is a clock management apparatus wherein the clock management apparatus includes a clock synchronization signal generator, a plurality of clock gating units and clock frequency division modules; a synchronization signal of a predetermined period is generated by the clock synchronization signal generator; each of the clock gating units is connected in series with a corresponding one of the clock frequency division modules to form a signal processing branch; and the signal processing branches are connected in parallel to receive a source clock signal respectively, the clock gating unit controls the on-off switch of the signal processing branch, and the clock frequency division modules are configured to perform phase adjustment on the clock signals of the signal processing branches after receiving the synchronization signal output by the clock synchronization signal generator, and to adjust the clock signals of the signal processing branches from an asynchronous state to a synchronous state.
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公开(公告)号：US11973497B1
公开(公告)日：2024-04-30
申请号：US18050187
申请日：2022-10-27
Applicant: Synopsys, Inc.
Inventor： Jamil Kawa , Stephen Robert Whiteley , Eric M. Mlinar
Abstract: A parameterized superconducting circuit may include a set of sub-blocks which include superconducting circuitry. Different sub-blocks in the set of sub-blocks may be clocked using clock signals having different phases. Along a first direction, relative locations of the set of sub-blocks may be fixed. Along a second direction, relative locations of the set of sub-blocks may be determined based on a set of parameter values.
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公开(公告)号：US20240128977A1
公开(公告)日：2024-04-18
申请号：US18161103
申请日：2023-01-30
Applicant: Shaoxing Yuanfang Semiconductor Co., Ltd.
Inventor： Arnold J D'Souza , Shyam Somayajula
IPC: H03K19/0185 , H02M1/08 , H02M3/155 , H03K3/037 , H03K17/687 , H03K19/20
CPC classification number: H03K19/01855 , H02M1/08 , H02M3/155 , H03K3/037 , H03K17/687 , H03K19/20 , H03K2217/0063 , H03K2217/0072
Abstract: Aspects of the present disclosure provide level-shifters and their use with switching converters. A level-shifter receives a binary signal on an input node and generates an output signal also representing the same logic level of the binary signal. The output signal represents logic levels in a first voltage range defined with respect to a first constant reference potential in a sequence of first phases of a clock signal and in a second voltage range defined with respect to a second constant reference potential in a sequence of second phases of the clock signal. The first constant reference potential is lower than the second constant reference potential. A controller block contained in the level-shifter receives the binary signal and transfers a changed logic level of the binary signal only in the first phase, but not in the second phase of the clock signal.
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公开(公告)号：US20240128952A1
公开(公告)日：2024-04-18
申请号：US18377777
申请日：2023-10-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byounggon Kang , Dalhee Lee
IPC: H03K3/012 , G01R31/3185 , H03K3/037 , H03K19/20
CPC classification number: H03K3/012 , G01R31/318541 , H03K3/0372 , H03K19/20
Abstract: A low power flip-flop includes a master section including a multiplexer, a first AND-OR-Inverter (AOI) gate circuit, a second AOI gate circuit, and a first inverter circuit and configured to receive a data input signal, a scan input signal, a scan enable signal, and an inverted scan enable signal, and output a second internal signal and a third internal signal, a slave section including a third AOI gate circuit, a fourth AOI gate circuit, and a second inverter circuit, and configured to receive the second and third internal signals to output an output signal, and a third inverter circuit configured to generate the inverted scan enable signal. The first to fourth AOI gate circuits are configured to receive a clock signal.
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公开(公告)号：US20240128853A1
公开(公告)日：2024-04-18
申请号：US18145267
申请日：2022-12-22
Applicant: Richtek Technology Corporation
Inventor： Jung-Sheng CHEN , Chih-Chun CHUANG , Yong-Chin LEE
Abstract: A power converter that properly copes with the wiring defects on a feedback path is shown. According to a control signal, a power driver couples an input voltage to an energy storage element to provide an output voltage that is down-converted from the input voltage. The output voltage is further converted into a feedback voltage by a feedback circuit, and is entered to an error amplifier with a reference voltage for generation of an amplified error. A control signal generator generates the control signal of the power driver according to the amplified error. The power converter specifically has a comparator, which is enabled in a soft-start stage till the output voltage reaches a stable status. The comparator compares the amplified error with a critical value. When the amplified error exceeds the critical value, the input voltage is disconnected from the energy storage element.
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Patent Agency Ranking
56.发明授权公开(公告)号：US11962300B2
公开(公告)日：2024-04-16
申请号：US17160089
申请日：2021-01-27
Applicant: SK hynix Inc.
Inventor： Jaehyeong Hong , Yo Han Jeong , Jin Ha Hwang , Junseo Jang
CPC classification number: H03K3/017 , G06F1/04 , G06F1/26 , H03F3/45264 , H03K3/037
Abstract: An input/output circuit may include an input circuit, an amplifier circuit and a precharging circuit. The input circuit may load differential input data to setup nodes based on a data strobe clock. The amplifier circuit may compare and amplify the data that is loaded to the setup nodes and configured to output the amplified data. The precharging circuit may precharge the setup nodes based on the data strobe clock and the differential input data.
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公开(公告)号：US20240120916A1
公开(公告)日：2024-04-11
申请号：US18390301
申请日：2023-12-20
Applicant: IPGoal Microelectronics (Sichuan) Co., Ltd.
Inventor： Yalan Lv , Xiangyang Guo
Abstract: A power-on reset system includes a reset signal generator, a power-on reset module and a D flip-flop. The reset signal generator generates a reset enable signal when powered on, and the reset enable signal is input to the power-on reset module and the D flip-flop. An output end of the power-on reset module is connected with a clock end of the D flip-flop, an output end of the D flip-flop is connected with a control end of the power-on reset module, and an output signal of the power-on reset module controls the output reset signal of the D flip-flop. When a voltage of the enable end of the power-on reset module is a high level, the power-on reset module is turned off. In such a way, the entire power-on reset system generates no power consumption, thereby improving the working performance of the entire system chip.
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公开(公告)号：US11947672B2
公开(公告)日：2024-04-02
申请号：US17189329
申请日：2021-03-02
Applicant: NXP B.V.
Inventor： Andreas Bernardus Maria Jansman , Andreas Lentz
CPC classification number: G06F21/567 , G06F1/28 , G06F1/3296 , G06F21/81 , H03K3/0315 , H03K3/037 , H03K21/02 , G06F2221/034
Abstract: A voltage glitch detector includes a ring oscillator, a plurality of counters, a combined result circuit, and a result evaluation circuit. The ring oscillator includes a plurality of series-connected stages. An output of a last stage of the ring oscillator is coupled to an input of a first stage of the ring oscillator. Each counter of the plurality of counters has an input coupled to a node located between two stages of the plurality of series-connected stages. The combined result circuit is coupled to each of the plurality of counters. The combined result circuit combines the count values received from each counter of the plurality of counters to provide a combined result. The result evaluation circuit is coupled to compare the combined result with a reference value to determine when a voltage glitch is detected.
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公开(公告)号：US11942933B2
公开(公告)日：2024-03-26
申请号：US17521651
申请日：2021-11-08
Applicant: QUALCOMM Incorporated
Inventor： Wilson Jianbo Chen , Aliasgar Presswala , Chiew-Guan (Kelvin) Tan
IPC: H03K19/0185 , H03K3/037 , H03K19/003
CPC classification number: H03K19/018521 , H03K3/0375 , H03K19/00315
Abstract: An aspect of the disclosure relates to an apparatus including a first field effect transistor (FET) including a first gate configured to receive a first input signal that varies in accordance with a first voltage domain; and a first inverter including a first input configured to receive a second input signal that varies in accordance with a second voltage domain, and a first output configured to generate a first output signal that varies in accordance with the second voltage domain, wherein the first output signal is based on the first and second input signals, and wherein the first FET and the first inverter are coupled in series between first and second voltage rails. Per another aspect, the apparatus includes additional circuitry to allow the apparatus to process signals in accordance with a third voltage domain.
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公开(公告)号：US20240097302A1
公开(公告)日：2024-03-21
申请号：US18118271
申请日：2023-03-07
Inventor： Minoru NAGATA
Abstract: A digital isolator includes: an edge detection circuit configured to output a first detection signal and a second detection signal; a driving buffer circuit configured to output a first edge signal and a second edge signal; an isolation element configured to output a first edge signal and a second edge signal; a receiving inverter circuit configured to output a first reception signal and a second reception signal; a latch circuit configured to latch data based on the pulse of the first received signal and the pulse of the second received signal, and to output an output signal to an output terminal according to the data; a switch circuit configured to switch a state of conduction between the reference potential and the first output and a state of conduction between the reference potential and the second output; and a control circuit configured to control a switching operation.
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