公开(公告)号：US20200372198A1

公开(公告)日：2020-11-26

申请号：US16992930

申请日：2020-08-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： RAVI BABU PITTU ,  LI-CHUNG HSU ,  SUNG-YEN YEH ,  CHUNG-HSING WANG

IPC分类号： G06F30/3312 ,  G06F30/30 ,  G06F30/367

摘要： A method includes: identifying a timing path of a logic circuit; determining a Boolean expression at an internal node in the timing path; providing a DC vector having a plurality of forms; determining a Boolean value at the internal node for each of the forms based on the Boolean expression; determining a quantity of stressed transistors in the timing path for each of the forms separately based on the respective Boolean value; and determining a best-case form, associated with an aging effect of the logic circuit, and a worst-case form, associated with the aging effect, out of the forms based on the quantities of stressed transistors.

公开(公告)号：US10831954B1

公开(公告)日：2020-11-10

申请号：US16667880

申请日：2019-10-29

申请人： International Business Machines Corporation

发明人： Debjit Sinha ,  Ravi Chander Ledalla ,  Chaobo Li ,  Adil Bhanji ,  Gregory Schaeffer ,  Michael Hemsley Wood

IPC分类号： G06F17/50 ,  G06F30/30 ,  G06F30/398 ,  G06F30/3312 ,  G06F30/3323 ,  G06F30/373 ,  G06F30/337

摘要： Efficiency of electronic design automation is increased by accessing a data structure characterizing a hierarchical integrated circuit design including sub-blocks each with a plurality of ports. For each given one of the ports of each of the sub-blocks, obtain a wire specification for a corresponding net connected to the given one of the ports in the design, and based on the wire specification, consult a technology-specific lookup table to determine at least one of a corresponding default driving cell and default electrical model for an external wire coupling one of the default driving cell and an actual driving cell to the given one of the ports. Optimize each of the sub-blocks out-of-context based on the at least one of default driving cells and default electrical models; verify in-context closure for the optimized sub-blocks; and, responsive to the in-context closure, update the data structure to reflect the optimized sub-blocks.

公开(公告)号：US10796058B1

公开(公告)日：2020-10-06

申请号：US16141723

申请日：2018-09-25

申请人： Xilinx, Inc.

发明人： Nicholas A. Mezei ,  Steven Banks ,  Meiwei Wu ,  Raymond Kong

IPC分类号： G06F30/392 ,  G06F30/394 ,  G06F30/3312

摘要： A platform design including a module black-box instance is loaded into computer hardware. Using the computer hardware, synchronous boundary crossings between a static region and the module black-box instance of the platform design are identified and objects of the platform design included in the synchronous boundary crossings are marked. Using the computer hardware, unmarked objects are removed from the platform design to generate a shell circuit design. A custom circuit design is implemented based on the shell circuit design and timing constraints corresponding to objects remaining in the shell circuit design.

公开(公告)号：US10789406B1

公开(公告)日：2020-09-29

申请号：US16193803

申请日：2018-11-16

申请人： Cadence Design Systems, Inc.

发明人： Shiva Raja ,  Igor Keller ,  Ling Wang

IPC分类号： G06F30/3323 ,  G06F30/30 ,  G06F30/367 ,  G06F30/3312 ,  G06F111/04 ,  G06F111/10 ,  G06F111/20 ,  G06F119/12

摘要： The present embodiments are generally directed to electronic circuit design and verification and more particularly to techniques for characterizing electronic components within an electronic circuit design for use in verification. In one or more embodiments, an adaptive sensitivity based analysis is used to build an adaptive equation to represent the timing response surface for an electronic component. With the adaptive surface response built, a sample-based evaluation yields highly accurate extraction of electronic component timing parameters including on-chip variation information such as sigma and moments.

公开(公告)号：US20200302103A1

公开(公告)日：2020-09-24

申请号：US16823014

申请日：2020-03-18

申请人： Synopsys, Inc.

发明人： Cedric BABLED ,  Sylvain Bayon DE NOYER

IPC分类号： G06F30/3312 ,  G06F30/20

摘要： A hybrid electronic system including an emulator side including a processor and a first clock, a simulated side including one or more models to simulate one or more prototypes and a second clock, a first interface to the emulator side, and a second interface to the simulated side is disclosed. The processor is configured to determine using the first interface a first amount of time corresponding to an amount of time advanced on the emulator side by the first clock. The processor is configured to determine using the second interface a second amount of time corresponding to an amount of time advanced on the simulated side by the second clock, and set a value of a clock frequency of the second clock based on an initial value of the clock frequency of the second clock and a ratio of the first amount of time to the second amount of time.

公开(公告)号：US10776552B2

公开(公告)日：2020-09-15

申请号：US15823252

申请日：2017-11-27

申请人： Synopsys, Inc.

发明人： Victor Moroz ,  Ibrahim Avci ,  Shuqing Li ,  Philippe Roussel ,  Ivan Ciofi

IPC分类号： G06F30/394 ,  G06F30/33 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398 ,  G06F30/3312 ,  H01L29/06 ,  H01L23/50 ,  G06F111/10

摘要： An integrated circuit design tool for modeling resistance of an interconnect specifies a structure of the interconnect in a data structure in memory in or accessible by the computer system using 3D coordinate system. For each of a plurality of volume elements in the specified structure, the tool specifies a location and one of first and second materials of the interconnect having specified resistivities, and for each volume element generates a model resistivity for the volume element as a function of resistivity of volume elements within a neighborhood of the volume element and a specified transition region length λ.

公开(公告)号：US10762263B1

公开(公告)日：2020-09-01

申请号：US15988293

申请日：2018-05-24

申请人： Xilinx, Inc.

发明人： Roger Ng ,  David K. Liddell

IPC分类号： G06F30/3312 ,  G06F30/367 ,  G06F119/12

摘要： A method includes inputting to a computer processor a search value. Bit values of bit element signals of a bus at a current time are determined time-ordered value pairs of timestamps and associated bit values of the bit element signals. Whether the bit values at the current time match values of corresponding bits of the search value is determined from the time-ordered value pairs. Data indicative of the current time and bit values of the bit element signals is output if the bit values at the current time match the search value. If any of the bit values at the current time do not match the search value, the current time is advanced to a later time indicated by a time-ordered value pair not matched to the search value and having a latest timestamp of the bit element signals that do not match corresponding bits of the search value.

公开(公告)号：US10740519B2

公开(公告)日：2020-08-11

申请号：US15644760

申请日：2017-07-08

申请人： Nikolaos Zompakis

发明人： Nikolaos Zompakis

IPC分类号： G06F30/398 ,  G06F30/3312 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/324 ,  G06F30/327 ,  G06F30/394 ,  G06F111/04 ,  G06F119/12

摘要： The disclosure is directed to the design and manufacture of synchronous digital systems, such as integrated circuits (IC), to employ dynamic frequency boosting. The proposed technique overcomes limitations of conventional synchronous clock design by boosting operating clock frequency despite critical path time constraints and without violating the correct functionality. In accordance with an exemplary embodiment, ICs are configured to set the clock frequency during each state event by selecting a more optimum clock frequency, on a clock cycle basis, thus improving system performance in terms of throughput while maintaining the benefits and design approach of synchronous digital systems.

公开(公告)号：US10740518B2

公开(公告)日：2020-08-11

申请号：US16196992

申请日：2018-11-20

申请人： Amazon Technologies, Inc.

发明人： Islam Mohamed Hatem Abdulfattah Mohamed Atta

IPC分类号： G06F30/327 ,  G06F15/78 ,  G06F9/50 ,  G06F30/394 ,  G06F30/3312 ,  G06F16/22

摘要： The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include receiving a second request to download the configuration data to a host server computer comprising the configurable hardware. The method can include transmitting the configuration data to the host server computer in response to the second request so that the configurable hardware is configured with the host logic and the application logic.

公开(公告)号：US10726182B1

公开(公告)日：2020-07-28

申请号：US16100041

申请日：2018-08-09

申请人： Xilinx, Inc.

发明人： Sandeep S. Deshpande ,  Feng Cai ,  Saikat Bandyopadhyay

IPC分类号： G06F17/50 ,  G06F30/3312 ,  G06F9/448 ,  G06F30/327

摘要： Disclosed approaches involve simulating a circuit design specified in a hardware description language (HDL). During simulation, a thread is started at an edge of a simulation clock signal for evaluation of states of a finite state machine (FSM) that represent a series of events specified in a statement in the HDL. The thread transitions from one state to a next state in the FSM in response to evaluation of the one state. In response to encountering a fork state in the FSM, the thread is forked into two threads during simulation. The fork state represents a composite operator in the statement, and the FSM has a branch from the fork state for each operand of the composite operator. In response to encountering a join state in the FSM by the two threads, the two threads are joined into one thread.