公开(公告)号：US5515332A

公开(公告)日：1996-05-07

申请号：US391160

申请日：1995-02-21

Applicant: Luigi Pascucci ,  Marco Maccarrone ,  Marco Olivo

Inventor： Luigi Pascucci ,  Marco Maccarrone ,  Marco Olivo

IPC: G11C17/00 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32

CPC classification number: G11C7/02 ,  G11C16/32 ,  G11C7/1006 ,  G11C7/22

Abstract: A load timing circuit including an output simulation circuit similar to the output circuits of the memory, so as to present the same propagation delay; a simulating signal source for generating a data simulating signal; a synchronizing network for detecting a predetermined switching edge of the data simulating signal and enabling supply of the signal to the output simulation circuit and data supply to the output circuits of the memory; a combinatorial network for detecting propagation of the data simulating signal to the output of the output simulation circuit and disabling the data simulating signal; and a reset element for resetting the timing circuit.

Abstract translation: 一种负载定时电路，包括与存储器的输出电路相似的输出模拟电路，以便呈现相同的传播延迟; 用于产生数据模拟信号的模拟信号源; 同步网络，用于检测数据模拟信号的预定切换边沿，并且能够向输出模拟电路提供信号，并向存储器的输出电路提供数据; 组合网络，用于检测数据模拟信号的传播到输出模拟电路的输出，并禁用数据模拟信号; 以及用于复位定时电路的复位元件。

公开(公告)号：US5510947A

公开(公告)日：1996-04-23

申请号：US367747

申请日：1995-01-03

Applicant: Franco Pellegrini ,  Marco Morelli ,  Athos Canclini

Inventor： Franco Pellegrini ,  Marco Morelli ,  Athos Canclini

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H03K17/08 ,  H03K19/003 ,  H02H9/04

CPC classification number: H01L27/0248

Abstract: In an anti-ESD protective structure, especially designed for pins destined to reach below ground and/or above supply voltages, includes a pair of Zener diodes or lateral NPN structures with a resistive connection between base and emitter, connected in opposition among each other between the pin to be protected and a grounded substrate of the integrated circuit. An amplifying effect on the leakage current which is drawn/injected through the pin by the protective structure caused by the triggering of an intrinsic parasitic transistor is effectively eliminated by connecting a biasing element, such as a forward biased junction, between the node of interconnection between the two Zener orlateral NPN structures and a node of the integrated circuit biased with a voltage sufficiently high as to ensure, under any condition, a reverse biasing of the base-emitter junction of the parasitic transistor.

Abstract translation: 在防静电保护结构中，特别针对目的地达到低于地和/或高于电源电压的引脚设计，包括一对齐纳二极管或侧向NPN结构，其具有基极和发射极之间的电阻连接， 待保护的引脚和集成电路的接地基板。 通过在内部寄生晶体管的触发引起的保护结构通过引脚引出/注入的漏电流的放大效应通过在诸如正向偏置结之间的偏置元件之间连接在第 两个齐纳边的NPN结构和集成电路的一个节点，其偏压电压足够高，以确保在任何条件下寄生晶体管的基极 - 发射极的反偏置。

公开(公告)号：US5509069A

公开(公告)日：1996-04-16

申请号：US121294

申请日：1993-09-14

Applicant: Luciano Tomasini ,  Rinaldo Castello

Inventor： Luciano Tomasini ,  Rinaldo Castello

IPC: H04M19/08 ,  H04M19/00

CPC classification number: H04M19/08

Abstract: A circuit is provided in telecommunication terminal equipment for splitting a limited supply of current received from a subscriber's line current among a plurality of functional circuits according to their priority rank. The circuit uses a differential pair of current delivering transistors and a special circuit to monitor the actual current of absorption of at least the functional circuit of highest rank to produce a control signal that is used for modifying the drive conditions of the current delivering transistors. All current exceeding the actual absorption needs of the highest rank functional circuit is distributed to the other functional circuits and the prior art practice of sinking unneeded current through a dissipative shunt voltage regulator associated with each functional circuit is avoided. This same principle may be advantageously applied also to functional circuits of progressively lesser rank of priority.

Abstract translation: 在电信终端设备中提供电路，用于根据用户的线路电流根据其优先级排列从用户线路电流接收的有限供电电流。 该电路使用差分对的电流输送晶体管和专用电路来监视至少最高等级的功能电路的吸收的实际电流，以产生用于修改电流输送晶体管的驱动条件的控制信号。 超过最高等级功能电路的实际吸收需求的全部电流被分配到其他功能电路，并且避免了通过与每个功能电路相关联的耗散分流稳压器吸收不需要的电流的现有技术的实践。 该相同的原理也可以有利地应用于逐渐降低等级优先级的功能电路。

公开(公告)号：US5499217A

公开(公告)日：1996-03-12

申请号：US348461

申请日：1994-12-02

Applicant: Luigi Pascucci ,  Carla M. Golla ,  Marco Maccarrone

Inventor： Luigi Pascucci ,  Carla M. Golla ,  Marco Maccarrone

IPC: G11C17/00 ,  G11C8/10 ,  G11C16/06 ,  G11C8/00

CPC classification number: G11C8/10

Abstract: A memory line decoding driver is so biased that the P channel pull-up transistor biasing the final inverter conducts a high current during the line address transient phase, for rapidly charging the input of the final inverter, and is turned on weakly during the static phase between one address phase and another, for reducing current consumption. For which purpose, a voltage modulating stage alternatively connects the gate terminal of the pull-up transistor to a capacitor, with which the charge is distributed, and to the supply.

Abstract translation: 存储器线路解码驱动器被偏置，使得偏置最终的反相器的P沟道上拉晶体管在线路地址瞬态阶段期间导通高电流，以便对最终的反相器的输入进行快速充电，并且在静态期间弱 在一个地址阶段和另一个之间，以减少电流消耗。 为此，电压调制级将上拉晶体管的栅极端子交替地连接到电荷分配的电容器和电源。

公开(公告)号：US5497345A

公开(公告)日：1996-03-05

申请号：US196572

申请日：1994-02-15

Applicant: Paolo G. Cappelletti

Inventor： Paolo G. Cappelletti

IPC: G11C5/00 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC classification number: H01L27/11521 ,  G11C5/005 ,  H01L27/0255 ,  H01L27/115

Abstract: To protect the thin tunnel oxide layer interposed between the floating gate region of memory cells and the substrate and which are subject to in-process damage, when the wafer is subjected to radiation, provision is made for a diode, connected between the control gate region of the cells and the substrate. The diode defines a conductive path that, when normal operating voltage is applied to the control gate regions, is turned off and has no effect on normal operation of the memory, and which is turned on to permit the passage of charges between the control gate region and the substrate, when the control gate potential exceeds normal operating potential but is less than the breakdown voltage of the tunnel oxide divided by the coupling factor of the control and floating gate regions of the cells. The diode is appropriately formed prior to patterning the control gate regions of the cells.

Abstract translation: 为了保护插入在存储器单元的浮动栅极区域和衬底之间并且经受过程中损坏的薄隧道氧化物层，当晶片经受辐射时，提供连接在控制栅极区域之间的二极管 的细胞和底物。 二极管限定了当正常工作电压施加到控制栅极区域时被关闭并且对存储器的正常操作没有影响并且被导通以允许电荷在控制栅极区域之间通过的导电路径 并且当控制栅极电位超过正常工作电位但小于隧道氧化物的击穿电压除以电池的控制和浮动栅极区域的耦合因子时，衬底。 在对单元的控制栅极区域进行构图之前适当地形成二极管。

公开(公告)号：US5495201A

公开(公告)日：1996-02-27

申请号：US145989

申请日：1993-10-29

Applicant: Roberto Alini ,  Maurizio Zuffada ,  David Moloney ,  Silvano Gornati

Inventor： Roberto Alini ,  Maurizio Zuffada ,  David Moloney ,  Silvano Gornati

IPC: H03F1/32 ,  H03F3/45 ,  H03H11/04 ,  G06G7/12

CPC classification number: H03F3/45071 ,  H03F1/3211 ,  H03H11/0422

Abstract: A transconductor stage for high-frequency filters operated on a low voltage supply, being of a type which comprises an input circuit portion having signal inputs, further comprises a pair of interconnected differential cells (2,3) being associated each with a corresponding signal input. Each cell incorporates at least one pair of bipolar transistors (Q1,Q2;Q3,Q4) having at least one corresponding terminal thereof (e.g. the emitter terminal) connected in common.

Abstract translation: 一种用于在低电压电源上工作的高频滤波器的跨导电压级，其包括具有信号输入的输入电路部分的类型，还包括一对互连的差分单元（2,3），其中每一个具有对应的信号输入 。 每个单元包含至少一对具有共同连接的至少一个对应端子（例如发射极端子）的双极晶体管（Q1，Q2; Q3，Q4）。

公开(公告)号：US5493531A

公开(公告)日：1996-02-20

申请号：US350961

申请日：1994-12-07

Applicant: Luigi Pascucci ,  Marco Maccarrone

Inventor： Luigi Pascucci ,  Marco Maccarrone

IPC: G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC classification number: G11C29/789 ,  G11C29/835

Abstract: An integrated circuit for checking the utilization rate of redundancy memory elements in semiconductor memory device, comprising a matrix of memory elements and a redundancy circuitry which comprises a plurality of programmable non-volatile memory registers, each supplied with address signals to generate a redundancy selection signal for the selection of an associated redundancy memory element when the address signals coincide with the address stored therein, and combinatorial circuit means supplying the non-volatile memory registers with an inhibition signal for inhibiting the generation of the respective redundancy selection signals when the address signals coincide with the address stored in a non-programmed non-volatile memory register; the integrated circuitry comprises multiplexing circuit means, controlled by a control signal generated by a control circuitry of the memory device, for transmitting the redundancy selection signals to output pads of the memory device when the control signal is activated; the control signal is also supplied to said combinatorial circuit means to prevent when activated the generation of said inhibition signal.

Abstract translation: 一种用于检查半导体存储器件中的冗余存储器元件的利用率的集成电路，包括存储器元件矩阵和冗余电路，该冗余电路包括多个可编程非易失性存储器寄存器，每个被提供有地址信号以产生冗余选择信号 用于当地址信号与存储在其中的地址一致时选择相关联的冗余存储器元件，组合电路装置为非易失性存储器寄存器提供禁止信号，以在地址信号一致时禁止生成相应的冗余选择信号 地址存储在非编程的非易失性存储器寄存器中; 集成电路包括由控制信号控制的多路复用电路装置，该控制信号由存储器件的控制电路产生，用于当控制信号被激活时，将冗余选择信号发送到存储器件的输出焊盘; 控制信号也被提供给所述组合电路装置，以防止当被激活时产生所述抑制信号。

公开(公告)号：US5493141A

公开(公告)日：1996-02-20

申请号：US231071

申请日：1994-04-21

Applicant: Bruno Ricco ,  Massimo Lanzoni ,  Luciano Briozzo

Inventor： Bruno Ricco ,  Massimo Lanzoni ,  Luciano Briozzo

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/12 ,  G11C16/14 ,  G11C16/34 ,  G11C16/06

CPC classification number: G11C16/3477 ,  G11C16/12 ,  G11C16/14 ,  G11C16/3468 ,  G11C16/3486

Abstract: The present programming method exploits the close dependence of tunneling current on the voltage drop across the tunnel oxide layer. A bootstrapped capacitor connected to the drain terminal of the transistor is employed. The charge state of the capacitor determines the bias of the tunnel oxide and is in turn determined by the charge state in the floating gate. Biasing by the bootstrapped capacitor is such as to permit passage of the tunneling current and, hence, a change in the threshold voltage of the transistor until the floating gate reaches the desired charge level, and to prevent passage of the tunneling current upon the transistor reaching the desired threshold. Programming is thus performed automatically and to a predetermined degree of accuracy, with no need for a special circuit for arresting the programming operation when the desired threshold is reached.

Abstract translation: 目前的编程方法利用了隧穿电流对隧道氧化物层两端的电压降的紧密依赖性。 使用连接到晶体管的漏极端子的自举电容器。 电容器的充电状态决定了隧道氧化物的偏压，又由浮栅中的电荷状态确定。 通过自举电容器的偏置使得能够通过隧道电流，从而允许晶体管的阈值电压的变化，直到浮栅达到期望的电荷水平，并且防止隧道电流在晶体管达到时通过 所需的阈值。 因此，自动执行编程并达到预定的准确度，当达到期望的阈值时，不需要用于阻止编程操作的特殊电路。

公开(公告)号：US5469389A

公开(公告)日：1995-11-21

申请号：US219204

申请日：1994-03-29

Applicant: Marco Olivo ,  Luigi Pascucci

Inventor： Marco Olivo ,  Luigi Pascucci

IPC: G11C29/00 ,  G11C11/00 ,  G11C29/04

CPC classification number: G11C11/00

Abstract: There is described a semiconductor memory including a matrix of rows and columns of memory cells, wherein the columns are grouped together in sectors, each sector representing the portion of the matrix itself related to a data input/output line. Each sector is in turn divided into packets of columns, and there are redundancy columns suitable for replacing a matrix column containing defective memory cells. Each of the redundancy columns is included in a respective packet. The memory also includes control circuits to execute the abovementioned replacement.

Abstract translation: 描述了包括存储器单元的行和列的矩阵的半导体存储器，其中列被分组在扇区中，每个扇区表示矩阵本身与数据输入/输出线相关的部分。 每个扇区又被分成列的分组，并且存在适于替换包含有缺陷的存储单元的矩阵列的冗余列。 每个冗余列被包括在相应的分组中。 存储器还包括执行上述替换的控制电路。

公开(公告)号：US5467358A

公开(公告)日：1995-11-14

申请号：US943186

申请日：1992-09-10

Applicant: Flavio Scarra

Inventor： Flavio Scarra

IPC: G06F11/22 ,  G06F15/78 ,  G11C29/16 ,  G11C29/20 ,  H04B17/00

CPC classification number: G11C29/20 ,  G11C29/16

Abstract: A process for checking, reading or writing memories of a programmed computer. The process selects a pre-selected logic space in a memory to be checked. The process triggers the addressing micro-instructions of a suitable micro-program related to a pre-selected checking procedure, so as to cause its execution by means of a pre-established number of clock strokes. The micro-instructions of the micro-program are executed according to an incremental sequence and repeated in a loop.

Abstract translation: 用于检查，读取或写入编程计算机的存储器的过程。 该过程选择要检查的存储器中的预选逻辑空间。 该过程触发与预先选择的检查过程相关的合适的微程序的寻址微指令，以便通过预定数量的时钟行程使其执行。 根据增量序列执行微程序的微指令，并循环重复。