公开(公告)号：US10535393B1

公开(公告)日：2020-01-14

申请号：US16041778

申请日：2018-07-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan

IPC: G11C11/406 ,  G11C11/409

Abstract: An electronic device including a memory functional block having multiple ranks of memory and a memory controller functional block coupled to the memory. The memory controller includes refresh logic that detects, based on buffered memory accesses for each rank of memory of the ranks of memory, two or more ranks of memory for which a refresh is to be performed during a refresh interval. Based at least in part on one or more properties of buffered memory accesses for the two or more ranks of memory, the refresh logic determines a refresh order for performing refreshes for the two or more ranks of memory during the refresh interval. The memory controller then performs, in the refresh order, refreshes for the two or more ranks of memory during the refresh interval.

公开(公告)号：US20200005514A1

公开(公告)日：2020-01-02

申请号：US16023387

申请日：2018-06-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ruijin Wu ,  Skyler Jonathon Saleh ,  Christopher J. Brennan ,  Kei Ming Kwong ,  Anthony Hung-Cheong Chan

IPC: G06T15/00 ,  G06T9/00 ,  G09G3/00 ,  G06T7/90

Abstract: A technique for compressing an original image is disclosed. According to the technique, an original image is obtained and a delta-encoded image is generated based on the original image. Next, a segregated image is generated based on the delta-encoded image and then the segregated image is compressed to produce a compressed image. The segregated image is generated because the segregated image may be compressed more efficiently than the original image and the delta image.

公开(公告)号：US10523428B2

公开(公告)日：2019-12-31

申请号：US15820539

申请日：2017-11-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Gongyuan Zhuang ,  Thomas R. Woller

IPC: H04L9/08 ,  H04L9/14 ,  H04L9/30

Abstract: A method and apparatus provides cryptographic keys using, for example, a cryptographic co-processor (CCP) that uses spare processor cycles to work on cryptographic key generation in advance of the keys being needed by a requestor such as an application, or other process in the device. In one example, the cryptographic co-processor detects an idle condition of the CCP such as an idle condition of a cryptographic engine in the CCP. Control logic causes the CCP to generate at least one asymmetric key component corresponding to an asymmetric cryptographic key in response to detecting the idle condition. The method and apparatus stores the asymmetric key component(s) in persistent memory and generates the asymmetric cryptographic key using the stored asymmetric key component that was generated in response to detection of the idle condition of the CCP.

公开(公告)号：US20190393123A1

公开(公告)日：2019-12-26

申请号：US16563077

申请日：2019-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC: H01L23/367 ,  H01L25/00 ,  H01L25/065

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

公开(公告)号：US20190384722A1

公开(公告)日：2019-12-19

申请号：US16007027

申请日：2018-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Michael LeBeane ,  Eric Van Tassell

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F9/50 ,  G06F9/48 ,  G06F13/16 ,  G06F13/22

Abstract: A data processing system includes a memory, a group of input/output (I/O) devices, an input/output memory management unit (IOMMU). The IOMMU is connected to the memory and adapted to allocate a hardware resource from among a group of hardware resources to receive an address translation request for a memory access from an I/O device. The IOMMU detects address translation requests from the plurality of I/O devices. The IOMMU reorders the address translation requests such that an order of dispatching an address translation request is based on a policy associated with the I/O device that is requesting the memory access. The IOMMU selectively allocates a hardware resource to the input/output device, based on the policy that is associated with the I/O device in response to the reordering.

公开(公告)号：US10510185B2

公开(公告)日：2019-12-17

申请号：US15687421

申请日：2017-08-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Skyler Jonathon Saleh ,  Christopher J. Brennan ,  Andrew S. Pomianowski ,  Ruijin Wu

IPC: G06T15/80 ,  G06T15/40 ,  G06T15/00 ,  G06T11/40

Abstract: A technique for performing rasterization and pixel shading with decoupled resolution is provided herein. The technique involves performing rasterization as normal to generate fine rasterization data and a set of (fine) quads. The quads are accumulated into a tile buffer and coarse quads are generated from the quads in the tile buffer based on a shading rate. The shading rate determines how many pixels of the fine quads are combined to generate coarse pixels of the coarse quads. Combination of fine pixels involves generating a single coarse pixel for each such fine pixel to be combined. The positions of the coarse pixels of the coarse quads are set based on the positions of the corresponding fine pixels. The coarse quads are shaded normally and the resulting shaded coarse quads are modified based on the fine rasterization data to generate shaded fine quads.

公开(公告)号：US10509596B2

公开(公告)日：2019-12-17

申请号：US15851476

申请日：2017-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov ,  Jiasheng Chen

IPC: G06F3/00 ,  G06F3/06 ,  G06T1/60 ,  G06T1/20 ,  G06F9/38

Abstract: A technique for accessing memory in an accelerated processing device coupled to stacked memory dies is provided herein. The technique includes receiving a memory access request from an execution unit and identifying whether the memory access request corresponds to memory cells of the stacked dies that are considered local to the execution unit or non-local. For local accesses, the access is made “directly”, that is, without using a bus. A control die coordinates operations for such local accesses, activating particular through-silicon-vias associated with the memory cells that include the data for the access. Non-local accesses are made via a distributed cache fabric and an interconnect bus in the control die. Various other features and details are provided below.

公开(公告)号：US20190371400A1

公开(公告)日：2019-12-05

申请号：US16533278

申请日：2019-08-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Amin FARMAHINI FARAHANI ,  David A. ROBERTS

IPC: G11C14/00 ,  H01L27/108 ,  G11C7/10

Abstract: A high-performance on-module caching architecture for hybrid memory modules is provided. A hybrid memory module includes a cache controller, a first volatile memory coupled to the cache controller, a first multiplexing data buffer coupled to the first volatile memory and the cache controller, and a first non-volatile memory coupled to the first multiplexing data buffer and the cache controller, wherein the first multiplexing data buffer multiplexes data between the first volatile memory and the first non-volatile memory and wherein the cache controller enables a tag checking operation to occur in parallel with a data movement operation. The hybrid memory module includes a volatile memory tag unit coupled to the cache controller, wherein the volatile memory tag unit includes a line connection that allows the cache controller to store a plurality of tags in the volatile memory tag unit and retrieve the plurality of tags from the volatile memory tag unit.

公开(公告)号：US10467138B2

公开(公告)日：2019-11-05

申请号：US14981833

申请日：2015-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul Blinzer ,  Ali Ibrahim ,  Benjamin T. Sander ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/0888 ,  G06F12/0815 ,  G06F12/0813 ,  H04L29/08

Abstract: A processing system includes a first socket, a second socket, and an interface between the first socket and the second socket. A first memory is associated with the first socket and a second memory is associated with the second socket. The processing system also includes a controller for the first memory. The controller is to receive a first request for a first memory transaction with the second memory and perform the first memory transaction along a path that includes the interface and bypasses at least one second cache associated with the second memory.

公开(公告)号：US20190332420A1

公开(公告)日：2019-10-31

申请号：US15965231

申请日：2018-04-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Yash Sanjeev Ukidave ,  John Kalamatianos ,  Bradford Michael Beckmann

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/52

Abstract: Systems, apparatuses, and methods for performing split-workgroup dispatch to multiple compute units are disclosed. A system includes at least a plurality of compute units, control logic, and a dispatch unit. The control logic monitors resource contention among the plurality of compute units and calculates a load-rating for each compute unit based on the resource contention. The dispatch unit receives workgroups for dispatch and determines how to dispatch workgroups to the plurality of compute units based on the calculated load-ratings. If a workgroup is unable to fit in a single compute unit based on the currently available resources of the compute units, the dispatch unit divides the workgroup into its individual wavefronts and dispatches wavefronts of the workgroup to different compute units. The dispatch unit determines how to dispatch the wavefronts to specific ones of the compute units based on the calculated load-ratings.