公开(公告)号：US12218860B2

公开(公告)日：2025-02-04

申请号：US16932765

申请日：2020-07-19

Applicant: Mellanox Technologies, Ltd.

Inventor： Gal Yefet ,  Avi Urman ,  Gil Kremer ,  Lior Narkis ,  Boris Pismenny

IPC: H04L49/90 ,  G06F9/54 ,  H04L47/2441 ,  H04L69/22

Abstract: A network node includes a network adapter and a host. The network adapter is coupled to a communication network. The host includes a processor running a client process and a communication stack, and is configured to receive packets from the communication network, and classify the received packets into respective flows that are associated with respective chunks in a receive buffer, to distribute payloads of the received packets among the chunks so that payloads of packets classified to a given flow are stored in a given chunk assigned to the given flow, and to notify the communication stack of the payloads in the given chunk, for transferring the payloads in the given chunk to the client process.

公开(公告)号：US12216604B2

公开(公告)日：2025-02-04

申请号：US17958111

申请日：2022-09-30

Applicant: Mellanox Technologies, Ltd.

Inventor： Rui Xu ,  Mark Rosenbluth ,  Diane Orf ,  Michael Cotsford ,  Shreya Tekade

IPC: G06F13/00 ,  G06F13/24 ,  G06F13/40

Abstract: A virtual wire system includes a source device, a target device, and a mesh interface connecting the source device and the target device. One or more mesh messages are transmitted over the mesh interface from the source device to the target device, and the one or more mesh messages indicate a change in a value of a signal level at the source device. The source device may include a plurality of virtual wire sources, a virtual wire encoder, and a virtual wire arbiter operatively coupled to the plurality of virtual wire sources and the virtual wire encoder. The virtual wire arbiter is configured to determine whether information from a virtual wire source should be transmitted to the virtual wire encoder. The virtual wire encoder is configured to receive information from the virtual wire arbiter, combine the information into a single virtual wire message, and transmit the single virtual wire message to a first mesh interface component in the source device.

公开(公告)号：US20250039097A1

公开(公告)日：2025-01-30

申请号：US18226587

申请日：2023-07-26

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Amit Kazimirsky ,  Eran Gil Beracha ,  Liron Mula ,  Aviv Kfir ,  Barak Gafni

IPC: H04L47/129 ,  H04L47/30

Abstract: A device, communication system, and method are provided. In one example, a system for routing traffic is described that includes a plurality of ports to facilitate communication over a network. The system also includes a controller to selectively activate or deactivate ports of the system based on queue depths and additional information to improve power efficiency of the system.

公开(公告)号：US20250039078A1

公开(公告)日：2025-01-30

申请号：US18917976

申请日：2024-10-16

Applicant: Mellanox Technologies, Ltd.

Inventor： Barak Gafni ,  Donald Bruce Sharp

IPC: H04L45/122 ,  H04L45/121 ,  H04L45/24

Abstract: An example method for dynamic packet routing using prioritized groups includes: receiving, by a node, a network packet to be forwarded to a network destination, identifying, based on data stored in a forwarding information data structure of the node, a first path satisfying a first cost criterion to the network destination, determining that a path latency of the first path exceeds a threshold latency, selecting, based on the data stored in the forwarding information data structure of the node, a second path to the network destination, wherein the second path satisfies a second cost criterion and does not satisfy the first cost criterion, and forwarding, by the node, the network packet to the network destination via a local interface associated with the second path.

公开(公告)号：US20250036391A1

公开(公告)日：2025-01-30

申请号：US18911312

申请日：2024-10-10

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Yair Chasdai

IPC: G06F8/65 ,  G06F13/10

Abstract: A peripheral device includes a bus interface, a first processor and a second processor. The bus interface is to communicate over a peripheral bus. The first processor is to manage communication over the peripheral bus by executing bus-maintenance software code, the bus-maintenance software code being executed from one or more first layers of a multi-layer memory. The second processor is to update the bus-maintenance software code from an existing version to an updated version, by (i) loading the updated version to one or more second layers of the multi-layer memory, higher in hierarchy than the or one more first layers, and (ii) invalidating the existing version in the one or more first layers, thereby forcing fetching of the updated version from the one or more second layers to the one or more first layers and to start executing the updated version.

公开(公告)号：US20250035965A1

公开(公告)日：2025-01-30

申请号：US18911975

申请日：2024-10-10

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Oren STEINBERG ,  Anders Gösta LARSSON ,  Attila FÜLÖP ,  Elad MENTOVICH ,  Isabelle CESTIER ,  Moshe B. ORON

IPC: G02F1/017 ,  G02F1/015 ,  H01L31/0232 ,  H01L31/0304 ,  H01L31/109

Abstract: Processes and devices for continuous compositional grading in photodetectors and electro-absorption modulators (EAM) are provided. An example photodetector includes a multi-layered structure comprising a collector region, an absorber region, a grading layer, and a peripheral layer, all aligned along a detection axis. The grading layer, positioned adjacent to the absorber region, includes multiple sub-layers that define a continuous compositional grading to facilitate smooth carrier transport and reduce recombination. Similarly, an example electro-absorption modulator (EAM) device includes a waveguide mesa formed on a semiconductor substrate, comprising a multi-quantum well (MQW) core layer, upper and lower near-core cladding layers, and upper and lower central cladding layers. The EAM device features both upper and lower grading layers, each positioned between the near-core cladding layers and the adjacent central cladding layers. These grading layers include multiple sub-layers that define a continuous compositional grading, facilitating smooth transitions between the MQW core and surrounding cladding layers.

公开(公告)号：US20250024606A1

公开(公告)日：2025-01-16

申请号：US18904428

申请日：2024-10-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Xiuzhuang YANG ,  Huiying CHEN ,  Weibin HE ,  Di WU

IPC: H05K1/14 ,  H01G4/38 ,  H05K1/11 ,  H05K1/18 ,  H05K3/34

Abstract: Electronic devices, electronic modules, and methods for manufacturing electronic devices and/or electronic modules are described herein. In some embodiments, the present invention may be directed to an electronic module that includes a pair of printed circuit boards (PCBs) and a capacitor positioned between the PCBs. Each of the PCBs may include a pair of vias configured to provide electrical connections through the PCB, and the capacitor may include a pair of pins. Each pin of the capacitor may be aligned with a via of one of the PCBs and a corresponding via of the other PCB such that each pin is configured to provide electrical connection between the two PCBs. Additionally, the pair of pins may be configured to support the PCBs with respect to each other.

公开(公告)号：US20250021130A1

公开(公告)日：2025-01-16

申请号：US18349976

申请日：2023-07-11

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Maciej Machnikowski

IPC: G06F1/12

Abstract: In one embodiment, a system including a reference processing device includes a reference hardware clock to maintain a reference clock value, and reference clock synchronization circuitry to discipline the reference hardware clock responsively to a remote clock, which is remote to the system, and a follower processing device including a follower hardware clock to maintain a follower clock value, and follower clock synchronization circuitry to synchronize the follower hardware clock to the reference hardware clock, and provide an indication about the follower clock value to the reference processing device, wherein the reference clock synchronization circuitry is configured to monitor a quality of the synchronization of the follower hardware clock to the reference hardware clock.

公开(公告)号：US20250013499A1

公开(公告)日：2025-01-09

申请号：US18218555

申请日：2023-07-05

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Noam Michaelis ,  Itamar Rabenstein ,  Ofir Klara Altshul ,  Idan Matari ,  Aviv Avraham Paxton ,  Nechami Sternfeld ,  Inbar Adler

IPC: G06F9/50

Abstract: A network device, system, and method are provided. An illustrative network device includes a plurality of ports connectable to a communication network, one or more reduction units decoupled from the plurality of ports, and configurable logic to service packet transmission between the one or more reduction units and the plurality of ports.

公开(公告)号：US20250012971A1

公开(公告)日：2025-01-09

申请号：US18887611

申请日：2024-09-17

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Elad MENTOVICH ,  Dimitrios KALAVROUZIOTIS ,  Jonathan LUFF ,  Wei QIAN ,  Dazeng FENG

IPC: G02B6/122 ,  G02B6/12 ,  G02B6/30 ,  G02F1/015

Abstract: An optical interconnect device and the method of fabricating it are described. The device includes an in-plane laser cavity transmitting a light beam along a first direction, a Franz Keldysh (FK) optical modulator transmitting the light beam along the first direction, a mode-transfer module including a tapered structure disposed after the FK optical modulator along the first direction to enlarge the spot size of the light beam to match an external optical fiber and a universal coupler controlling the light direction. The tapered structure can be made linear or non-linear along the first direction. The universal coupler passes the laser light to an in-plane external optical fiber if the fiber is placed along the first direction, or it is a vertical coupler in the case that the external optical fiber is placed perpendicularly to the substrate surface. The coupler is coated with highly reflective material.