公开(公告)号：US20210011080A1

公开(公告)日：2021-01-14

申请号：US16506264

申请日：2019-07-09

Applicant: STMicroelectronics International N.V.

Inventor： Rajesh Narwal ,  Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: G01R31/30 ,  G01R31/3173 ,  G01R31/317 ,  G01R31/319

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.

公开(公告)号：US10890619B2

公开(公告)日：2021-01-12

申请号：US16505174

申请日：2019-07-08

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma

IPC: G01R31/317 ,  G01R31/3185

Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.

公开(公告)号：US10886931B1

公开(公告)日：2021-01-05

申请号：US16937955

申请日：2020-07-24

Applicant: STMicroelectronics International N.V.

Inventor： Rajesh Narwal ,  Kavindu Shekhar Benjwal

IPC: H03M1/00 ,  H03M1/12 ,  H03K3/037 ,  H03K19/20

Abstract: A circuit includes analog input nodes and switches selectively coupling each of the analog input nodes to a capacitive node. Each of the switches is controlled by a respective bit of a channel selection word. Level shifting circuits are respectively coupled in parallel with the switches. A sampling capacitor is coupled between an output node and ground, the output node being coupled to the capacitive node. An analog to digital converter operates to digitize voltages at the output node.

公开(公告)号：US10811873B2

公开(公告)日：2020-10-20

申请号：US15823863

申请日：2017-11-28

Applicant: STMicroelectronics International N.V.

Inventor： Vicky Batra ,  Radhakrishnan Sithanandam

IPC: H02H9/04 ,  H01L27/02 ,  H01L27/06 ,  H01L23/528 ,  H02H9/00 ,  H01L27/04 ,  H02H3/22

Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit formed by an ESD event actuated transistor device. A bias current is generated in response to operation of a voltage independent current generator circuit. The bias current is sourced to ensure that the transistor device is deactuated after the ESD event is dissipated.

公开(公告)号：US20200327927A1

公开(公告)日：2020-10-15

申请号：US16809006

申请日：2020-03-04

Applicant: STMicroelectronics International N.V.

Inventor： Ashish KUMAR ,  Mohammad Aftab ALAM

IPC: G11C11/4099 ,  G11C11/4074 ,  G11C11/413 ,  G11C5/14

Abstract: A memory device includes a memory array powered between a virtual supply and virtual ground nodes. A dummy memory array is powered between first and second nodes. A virtual supply generation circuit generates a virtual supply voltage at the virtual supply node as a function of a first control voltage. A virtual ground generation circuit generates a virtual ground at the virtual ground node as a function of a second control voltage. A first control voltage generation circuit coupled between the first node and a power supply voltage generates the first control voltage as tracking retention noise margin (RNM) of the memory array, the first control voltage falling as the RNM decreases. A second control voltage generation circuit coupled between the second node and ground generates the second control voltage as tracking RNM of the memory array, the second control voltage rising as the RNM decreases.

公开(公告)号：US10802077B1

公开(公告)日：2020-10-13

申请号：US16387809

申请日：2019-04-18

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Shiv Kumar Vats ,  Himanshu

IPC: G01R31/3185 ,  G01R31/3183 ,  G01R31/3187

Abstract: A test circuit includes a BIST clock generator and a functional clock generator. A first multiplexer selectively passes the BIST clock or the functional clock as a selected clock in response to a clock selection signal. BIST logic operates based upon the BIST clock. Functional logic operating based upon the functional clock signal. A memory operates based upon the selected clock. When the test circuit is operating in BIST mode, a clock selection circuit receives and passes a BIST signal as the clock selection signal. When the test circuit is operating in a shift phase of a scan test mode, it generates the clock selection signal as asserted, and when the test circuit is operating in the capture phase of the scan test mode, it generates the clock signal as equal to a last bit received from a scan chain.

公开(公告)号：US20200310758A1

公开(公告)日：2020-10-01

申请号：US16833353

申请日：2020-03-27

Applicant: STMICROELECTRONICS S.R.L. ,  STMicroelectronics International N.V.

Inventor： Giuseppe DESOLI ,  Thomas BOESCH ,  Carmine CAPPETTA ,  Ugo Maria IANNUZZI

IPC: G06F7/544 ,  G06N3/04

Abstract: A Multiple Accumulate (MAC) hardware accelerator includes a plurality of multipliers. The plurality of multipliers multiply a digit-serial input having a plurality of digits by a parallel input having a plurality of bits by sequentially multiplying individual digits of the digit-serial input by the plurality of bits of the parallel input. A result is generated based on the multiplication of the digit-serial input by the parallel input. An accelerator framework may include multiple MAC hardware accelerators, and may be used to implement a convolutional neural network. The MAC hardware accelerators may multiple an input weight by an input feature by sequentially multiplying individual digits of the input weight by the input feature.

公开(公告)号：US10778082B2

公开(公告)日：2020-09-15

申请号：US16003331

申请日：2018-06-08

Applicant: STMicroelectronics International N.V.

Inventor： Akshat Jain

IPC: H05B6/06 ,  H05B6/12 ,  H02H3/20 ,  H02H7/10 ,  H02M1/32 ,  H03K17/082 ,  H05B6/10 ,  H02M1/08 ,  H02M7/04

Abstract: Disclosed herein is a circuit including a transistor, with a resonant tank coupled between a DC supply node and a first conduction terminal of the transistor. A gate driver generates a gate drive signal for biasing a control terminal of the transistor to cause it to conduct current through the resonant tank. Control circuitry monitors a voltage across the transistor to determine that the transistor is an overvoltage condition if that voltage exceeds a threshold, and monitors a current through the transistor to determine that the transistor is an overcurrent condition if that current exceeds a threshold. If overvoltage is determined, the control circuitry causes the gate driver to pull up the gate drive signal. If overcurrent is determined, the control circuitry causes the gate driver to pull down the gate drive signal. If either overvoltage or overcurrent is present, a pulse width of the gate drive signal is reduced.

公开(公告)号：US10759168B2

公开(公告)日：2020-09-01

申请号：US16357077

申请日：2019-03-18

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Simon Dodd ,  David S. Hunt ,  Joseph Edward Scheffelin ,  Dana Gruenbacher ,  Stefan H. Hollinger ,  Uwe Schober ,  Peter Janouch

IPC: B41J2/14 ,  B41J2/175

Abstract: The present disclosure provides supports for microfluidic die that allow for nozzles of the microfluidic die to be on a different plane or face a different direction from electrical contacts on the same support. This includes a rigid support having electrical contacts on a different side of the rigid support with respect to a direction of ejection of the nozzles, and a semi-flexible support or semi-rigid support that allow the electrical contacts to be moved with respect to a direction of ejection of the nozzles. The semi-flexible and semi-rigid supports allow the die to be up to and beyond a 90 degree angle with respect to a plane of the electrical contacts. The different supports allow for a variety of positions of the microfluidic die with respect to a position of the electrical contacts.

公开(公告)号：US10747282B2

公开(公告)日：2020-08-18

申请号：US16162543

申请日：2018-10-17

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla ,  Sandip Atal

IPC: G06F1/24 ,  H03K19/00 ,  G01R31/319 ,  G06F1/3206 ,  H03K17/22

Abstract: An electronic device includes a power management circuit generating output for a plurality of voltage monitors that each detect whether voltages received from a test apparatus are at least a different minimum threshold. The power management circuit also generates a test enable signal indicative of whether the test apparatus is supplying the minimum required voltages to the electronic device. A control circuit receives the output for the plurality of voltage monitors and the test enable signal and generates at least one control signal as a function of the output for the plurality of voltage monitors and the test enable signal. An output circuit receives the at least one control signal and generates an interface control signal that selectively enables or disables interface with analog intellectual property packages within the electronic device, in response to the at least one control signal.