公开(公告)号：US10147673B2

公开(公告)日：2018-12-04

申请号：US15281800

申请日：2016-09-30

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Talledo

IPC: H01L23/49 ,  H01L23/498 ,  H01L23/495 ,  H01L21/48

Abstract: The present disclosure is directed to a semiconductor die on a tapeless leadframe and covered in encapsulant. The semiconductor package includes leads formed from the leadframe and electrically coupled to the semiconductor die, the leads being accessible through electrical contacts embedded in the encapsulant. Openings between the leads and the leadframe are formed from etching recesses from opposing sides of the leadframe. The resulting openings have non-uniform sidewalls. The leadframe is further electrically or thermally coupled to electrical contacts embedded in the encapsulant. The embedded electrical contacts forming a land grid array.

公开(公告)号：US10137794B2

公开(公告)日：2018-11-27

申请号：US14839447

申请日：2015-08-28

Applicant: STMicroelectronics, Inc.

Inventor： Oleg Logvinov ,  Bo Zhang ,  James D. Allen

IPC: H02J7/00 ,  B60L11/18

Abstract: An embodiment is a system including a first wireless charging pad coupled to a wireless charging system and an energy source, the first wireless charging pad being configured to transmit an energy by a magnetic field. The system further includes a second wireless charging pad coupled to a second system, the second wireless charging pad configured to receive at least a portion of the energy from the first wireless charging system for operating the second system. Further embodiments include a least one of an electronic compass configured to provide alignment data of the first and second wireless charging pads, and an interface configured to receive the alignment data and affect an alignment of the first and second wireless charging pads.

公开(公告)号：US10134895B2

公开(公告)日：2018-11-20

申请号：US13692632

申请日：2012-12-03

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/161

Abstract: The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended.

公开(公告)号：US10128169B1

公开(公告)日：2018-11-13

申请号：US15594351

申请日：2017-05-12

Applicant: STMicroelectronics, Inc.

Inventor： Aaron Cadag ,  Ian Harvey Arellano ,  Ela Mia Cadag

IPC: H01L21/44 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/49513 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/315 ,  H01L23/4952 ,  H01L23/49541 ,  H01L24/32 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2221/68381 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/92247

Abstract: A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process.

公开(公告)号：US10103174B2

公开(公告)日：2018-10-16

申请号：US14964648

申请日：2015-12-10

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Qing Liu ,  Nicolas Loubet

IPC: H01L27/092 ,  H01L27/12 ,  H01L21/84 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8238

Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.

公开(公告)号：US10096093B2

公开(公告)日：2018-10-09

申请号：US15592969

申请日：2017-05-11

Applicant: STMicroelectronics, Inc.

Inventor： Gordon Petrides

IPC: H04N7/00 ,  G06T5/00 ,  H04N7/01 ,  G06T5/20 ,  G06T7/20

Abstract: In one embodiment of the present invention, a method is provided for performing motion compensated interpolation using a previous frame and a current frame of a displayable output, the method comprising: detecting the speed of an object in the displayable output relative to the speed of a background in the displayable output; and blending results from a halo reducing interpolator and a median interpolator, wherein the results of each of the interpolators are weighted based on the speed of the object, to arrive at an interpolated frame using the previous frame and the current frame.

公开(公告)号：US10074606B2

公开(公告)日：2018-09-11

申请号：US15464487

申请日：2017-03-21

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L29/80 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/535

Abstract: A semiconductor substrate includes a doped region. A premetallization dielectric layer extends over the semiconductor substrate. A first metallization layer is disposed on a top surface of the premetallization dielectric layer. A metal contact extends from the first metallization layer to the doped region. The premetallization dielectric layer includes sub-layers, and the first metal contact is formed by sub-contacts, each sub-contact formed in one of the sub-layers. Each first sub-contact has a width and a length, wherein the lengths of the sub-contacts forming the metal contact are all different from each other.

公开(公告)号：US10038072B2

公开(公告)日：2018-07-31

申请号：US14982316

申请日：2015-12-29

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/775 ,  H01L21/66 ,  H01L29/45 ,  H01L29/778 ,  H01L29/41 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/66492 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823842 ,  H01L22/12 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/413 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66431 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7781 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

公开(公告)号：US10026849B2

公开(公告)日：2018-07-17

申请号：US15259516

申请日：2016-09-08

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC: H01L21/8234 ,  H01L27/146 ,  H01L29/786 ,  H01L29/66 ,  H01L29/24 ,  H01L29/49

Abstract: Processes and overturned thin film device structures generally include a metal gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the metal gate and the contacts can be self-aligned to the sacrificial material.

公开(公告)号：US10026830B2

公开(公告)日：2018-07-17

申请号：US14698921

申请日：2015-04-29

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Salih Muhsin Celik

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/51 ,  H01L29/06 ,  H01L29/739

Abstract: A tunneling field effect transistor is formed from a fin of semiconductor material on a support substrate. The fin of semiconductor material includes a source region, a drain region and a channel region between the source region and drain region. A gate electrode straddles over the fin at the channel region. Sidewall spacers are provided on each side of the gate electrode. The source of the transistor is made from an epitaxial germanium content source region grown from the source region of the fin and doped with a first conductivity type. The drain of the transistor is made from an epitaxial silicon content drain region grown from the drain region of the fin and doped with a second conductivity type.