公开(公告)号：US20040071007A1

公开(公告)日：2004-04-15

申请号：US10638949

申请日：2003-08-11

Applicant: STMicroelectronics SA

Inventor： Stephane Pecheyran ,  Jean-Michel Moragues ,  Benjamin Duval

IPC: G11C011/22

CPC classification number: G11C17/18 ,  G11C17/16

Abstract: An anti-fuse transistor includes a source, a drain and a well connected together, and a gate. A method for programming the anti-fuse transistor includes applying a reference potential to the gate, and applying a high potential greater than the reference potential to the drain of the anti-fuse transistor. A first access transistor is connected to the anti-fuse transistor. The first access transistor includes a drain connected to the source of the anti-fuse transistor, and a source for receiving the high potential. Applying the high potential to the drain of the anti-fuse transistor includes turning on the first access transistor.

Abstract translation: 反熔丝晶体管包括源极，漏极和阱连接在一起的栅极。 一种用于对抗熔丝晶体管进行编程的方法，包括向栅极施加参考电位，并将大于参考电位的高电位施加到反熔丝晶体管的漏极。 第一存取晶体管连接到反熔丝晶体管。 第一存取晶体管包括连接到反熔丝晶体管的源极的漏极和用于接收高电位的源极。 将高电位施加到反熔丝晶体管的漏极包括接通第一存取晶体管。

公开(公告)号：US20040070430A1

公开(公告)日：2004-04-15

申请号：US10641337

申请日：2003-08-14

Applicant: STMicroelectronics SA

Inventor： Francesco La Rosa

IPC: H03L007/00

CPC classification number: H03K17/223

Abstract: A power on reset circuit (POR) includes a first reset circuit for delivering a first reset signal when a supply voltage of the POR circuit is between a first low threshold and a first high threshold, and a second reset circuit for delivering a second reset signal when the supply voltage is between a second low threshold and a second high threshold. The second high threshold is less than the first high threshold. The POR circuit further includes at least one electrically erasable and programmable non-volatile memory cell. A delivery circuit outputs the first reset signal or the second reset based upon on whether the at least one electrically erasable and programmable non-volatile memory cell is in an erased or programmed state. The POR circuit has a threshold for outputting the first or second reset signal that is programmable according to the intended application.

Abstract translation: 上电复位电路（POR）包括第一复位电路，用于当POR电路的电源电压处于第一低阈值和第一高阈值之间时传送第一复位信号;以及第二复位电路，用于传送第二复位信号 当电源电压处于第二低阈值和第二高阈值之间时。 第二个高阈值小于第一个高阈值。 POR电路还包括至少一个电可擦除和可编程的非易失性存储单元。 输出电路基于至少一个电可擦除可编程非易失性存储单元是否处于擦除或编程状态来输出第一复位信号或第二复位。 POR电路具有用于输出根据预期应用可编程的第一或第二复位信号的阈值。

公开(公告)号：US20040057321A1

公开(公告)日：2004-03-25

申请号：US10611323

申请日：2003-07-01

Applicant: STMicroelectronics SA

Inventor： Helene Esch

IPC: G11C008/00

CPC classification number: G11C8/16

Abstract: The data storage device includes several registers that can be addressed by address words, and connected to p output ports through connections that can be configured in response to address words of p registers selected to read the contents of these registers on the p ports respectively. All register address words contain a specific bit with a predetermined rank identical for all address words and remaining bits. The registers are connected in pairs on each output port, each pair of registers containing two registers with address words that only differ in the value of the said specific bit. The connections include a pair of first switches that can be controlled in a complementary manner by the specific bit in the address word of one of the two registers, and a second switch connected to the output port considered and that can be controlled from the remaining bits of the address words of the two registers, for each pair of registers and for each output port, the first two switches are connected firstly between the corresponding two registers, and secondly between the corresponding second switch.

Abstract translation: 数据存储装置包括几个可由地址字寻址的寄存器，并通过可以配置为响应于p个寄存器的地址字被配置以读取p端口上的这些寄存器的内容的连接而连接到p个输出端口。 所有寄存器地址字包含具有与所有地址字和剩余位相同的预定秩的特定位。 寄存器在每个输出端口成对连接，每对寄存器包含两个寄存器，地址字仅在所述特定位的值上不同。 连接包括一对第一开关，其可以通过两个寄存器之一的地址字中的特定位以互补方式进行控制，第二开关连接到所考虑的输出端口，并且可以从剩余位 的两个寄存器的地址字，对于每对寄存器和每个输出端口，前两个开关首先连接在相应的两个寄存器之间，其次在相应的第二个开关之间连接。

公开(公告)号：US20040032243A1

公开(公告)日：2004-02-19

申请号：US10420342

申请日：2003-04-22

Applicant: STMicroelectronics SA

Inventor： Filipe Ganivet ,  Francesco La Rosa ,  Thierry Giovinazzi

IPC: G05F003/16

CPC classification number: G11C16/30 ,  G05F3/262 ,  G11C5/143 ,  G11C5/147 ,  H03K17/302

Abstract: A comparator compares a first voltage applied to a first input to a second voltage applied to a second input. The comparator delivers an output signal having a first value when the second voltage is higher than the first voltage, and having a second value when the second voltage is lower than the first voltage. The comparator includes first and second PMOS transistors arranged as current mirrors. The first PMOS transistor has its source connected to the first input of the comparator for receiving the first voltage. The second PMOS transistor has its source connected to the second input of the comparator for receiving the second voltage. The output of the comparator is connected to the drain of one of the transistors.

公开(公告)号：US20040028234A1

公开(公告)日：2004-02-12

申请号：US10606161

申请日：2003-06-25

Applicant: STMicroelectronics SA

Inventor： Sylvie Wuidart

IPC: H04K001/00

CPC classification number: G07F7/1008 ,  G06F7/00 ,  G06F21/72 ,  G06F21/75 ,  G06F2207/7223 ,  G06F2207/7266 ,  G06Q20/341 ,  G07F7/082

Abstract: Operation of a logic circuit for performing a desired logic function is scrambled. Logic gates and/or transistors are provided in the logic circuit so that the logic function is performed in at least two different ways. The way in which the logic function is performed is determined by the value of a function selection signal applied to the logic circuit. The function selection signal is random and is applied to the logic circuit, and the function selection signal is refreshed at determined instants for scrambling operation of the logic circuit. For identical data applied at the input of the logic circuit and for different values of the function selection signal, the polarities of certain internal nodes of the logic circuit and/or the current consumption of the logic circuit are not identical.

Abstract translation: 用于执行所需逻辑功能的逻辑电路的操作被加扰。 在逻辑电路中提供逻辑门和/或晶体管，使得以至少两种不同的方式执行逻辑功能。 执行逻辑功能的方式由施加到逻辑电路的功能选择信号的值决定。 功能选择信号是随机的，并且被施加到逻辑电路，并且在确定的时刻刷新功能选择信号以用于逻辑电路的加扰操作。 对于在逻辑电路的输入端应用的相同数据以及功能选择信号的不同值，逻辑电路的某些内部节点的极性和/或逻辑电路的电流消耗不相同。

公开(公告)号：US20040019814A1

公开(公告)日：2004-01-29

申请号：US10440044

申请日：2003-05-16

Applicant: STMicroelectronics SA ,  STMicroelectronics S.r.I.

Inventor： Francesco Pappalardo ,  Luigi Mantellassi

IPC: G06F001/26

CPC classification number: G06F9/30101 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  H01L23/34 ,  H01L2924/0002 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171 ,  H01L2924/00

Abstract: A system-on-chip (SoC) architecture includes a plurality of blocks, each including a power control module to selectively control the power dissipated by the bloc. For each block, a power register is provided to receive power control instructions to selectively control the respective power control module. The system also includes a power control unit for writing respective power control instructions into the power control registers of the blocks, whereby the power dissipated is controlled individually and independently for each block under the centralized control of the power control unit. For each block, a power status register is also provided to receive status information concerning power control within the respective block. The power control unit reads the status instructions from such power status registers.

Abstract translation: 片上系统（SoC）架构包括多个块，每个块包括功率控制模块，用于选择性地控制由该块所耗散的功率。 对于每个块，提供功率寄存器以接收功率控制指令以选择性地控制相应的功率控制模块。 该系统还包括用于将各个功率控制指令写入块的功率控制寄存器的功率控制单元，由此在功率控制单元的集中控制下，对每个块单独且独立地控制功率消耗。 对于每个块，还提供功率状态寄存器以接收关于相应块内的功率控制的状态信息。 电源控制单元从这些电源状态寄存器读取状态指令。

公开(公告)号：US20040010728A1

公开(公告)日：2004-01-15

申请号：US10438289

申请日：2003-05-13

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics SA

Inventor： Orazio Musumeci ,  Ahmed Kari

IPC: G06F001/12

CPC classification number: H03K5/19 ,  H03K5/1252 ,  H04L7/044

Abstract: A start-detection circuit and a stop-detection circuit detect the start condition and the stop condition in a data signal associated with a clock signal according to the IIC protocol. The start-detection circuit comprises: a first detector to produce a first reset signal when a trailing edge of the data signal is detected; a counter to count pulses of a reference signal when the first reset signal is received, and to produce an enabling signal when the number of pulses counted has reached a predefined number; a second detector to store the enabling signal when a trailing edge of the clock signal is detected. The stop-detection circuit comprises a third detector to produce a stop signal when a leading edge of the data signal is detected after the detection of a leading edge of the clock signal.

Abstract translation: 启动检测电路和停止检测电路根据IIC协议检测与时钟信号相关联的数据信号中的启动条件和停止条件。 启动检测电路包括：当检测到数据信号的后沿时产生第一复位信号的第一检测器; 计数器，当接收到第一复位信号时计数参考信号的脉冲，并且当计数的脉冲数达到预定数量时产生使能信号; 当检测到时钟信号的后沿时，存储启用信号的第二检测器。 停止检测电路包括第三检测器，当在检测到时钟信号的前沿之后检测到数据信号的前沿时产生停止信号。

公开(公告)号：US20030143796A1

公开(公告)日：2003-07-31

申请号：US10325609

申请日：2002-12-20

Applicant: STMicroelectronics SA

Inventor： Francesco La Rosa

IPC: H01L021/8238

CPC classification number: G05F3/262

Abstract: A current or voltage generator is integrated onto a silicon wafer and may include a first element including a first NMOS transistor having its source connected to ground through an electrical resistance, a second element including a second NMOS transistor having its source connected to ground, and a bias circuit for the first and second elements. The second element may include a voltage divider. The gate of the second NMOS transistor may be connected to a dividing node of the voltage divider, and the anode of the voltage divider may be connected to the gate of the first NMOS transistor. Both elements may be biased at an operating point corresponding to an identical temperature stability point for both elements.

Abstract translation: 电流或电压发生器被集成到硅晶片上，并且可以包括第一元件，其包括通过电阻将其源极连接到地的第一NMOS晶体管，包括其源极连接到地的第二NMOS晶体管的第二元件，以及 用于第一和第二元件的偏置电路。 第二元件可以包括分压器。 第二NMOS晶体管的栅极可以连接到分压器的分压节点，并且分压器的阳极可以连接到第一NMOS晶体管的栅极。 两个元件可能在对应于两个元件的相同温度稳定点的操作点处偏置。

公开(公告)号：US20240186090A1

公开(公告)日：2024-06-06

申请号：US18193230

申请日：2023-03-30

Applicant: STMICROELECTRONICS SA ,  STMicroelectronics (Crolles 2) SAS ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Philippe CATHELIN ,  Frederic GIANESELLO ,  Alain FLEURY ,  Stephane MONFRAY ,  Bruno REIG ,  Vincent PUYAL

IPC: H01H37/34 ,  H10N70/00 ,  H10N70/20

CPC classification number: H01H37/34 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8413 ,  H10N70/882

Abstract: The present description concerns a switch based on a phase-change material comprising: first, second, and third electrodes; a first region of said phase-change material coupling the first and second electrodes; and —a second region of said phase-change material coupling the second and third electrodes.

公开(公告)号：US20240118871A1

公开(公告)日：2024-04-11

申请号：US17961927

申请日：2022-10-07

Applicant: STMICROELECTRONICS SA

Inventor： Tarek BOCHKATI

IPC: G06F8/30

CPC classification number: G06F8/30

Abstract: System, method, and circuitry for generating a linker model for use by a toolchain associated with a programmable computing device. One or more regions in the memory resources available to the programmable computing devices is defined for used by an application executing on the programmable computing device. One or more sections is defined for those regions for use by the application. Resource boundaries are generated for the application based on the defined regions and the defined sections. A user is enabled to modify the defined regions or the defined sections or the generated resource boundaries. A linker model is then generated based on the available memory resources, the defined regions, the defined sections, and the generated resource boundaries. This linker model is then utilized to generate a linker script for the programmable computing device based the linker syntax compatible with a toolchain linker for the programmable computing device.