Method and apparatus for communicating with an access node

    公开(公告)号:US09667436B2

    公开(公告)日:2017-05-30

    申请号:US14916829

    申请日:2014-09-04

    CPC classification number: H04L12/2858 H04L12/2869

    Abstract: An access network comprises a plurality of access nodes (DSLAMs), a plurality of network access servers (CP BRASs) and an ANCP relay. The access network control relay component relays data between an access node and a plurality of network access servers and includes one or more interfaces and associated functionality in an ANCP listener component for enabling a connection between the relay component and the access node, for transmitting data and/or messages thereover, and an interface (ANCP Agents) for a connection to be made with each of the plurality of network access servers (via ANCP listeners contained within the BRASs) for transmitting ANCP messages thereover; and a mapping database for storing mapping data to determine to which network access server a message should be transmitted from the relay component, together with a CP authentication database and a workflow processing component for controlling operation of components within the ANCP relay.

    Method and devices for frequency distribution
    65.
    发明授权
    Method and devices for frequency distribution 有权
    频率分配方法和装置

    公开(公告)号:US09112631B2

    公开(公告)日:2015-08-18

    申请号:US14023815

    申请日:2013-09-11

    Abstract: This invention relates to methods and devices for frequency distribution based on, for example, the IEEE 1588 Precision Time Protocol (PTP). Packet delay variation (PDV) is a direct contributor to the noise in the recovered clock and various techniques have been proposed to mitigate its effects. Embodiments of the invention provide a mechanism to directly measure and remove PDV effects in the clock recovery mechanism at a slave clock. One particular embodiment provides a clock recovery mechanism including a phase-locked loop (PLL) with a PDV compensation feature built-in. An aim of the invention is to enable a slave clock to recover the master clock to a higher quality as if the communication path between master and slave is free of PDV. This technique may allow a packet network to provide clock synchronization services to the same level as time division multiplexing (TDM) networks and Global Positioning System (GPS).

    Abstract translation: 本发明涉及基于例如IEEE 1588精确时间协议(PTP)的用于频率分布的方法和装置。 分组延迟变化(PDV)是恢复时钟中的噪声的直接贡献者,并且已经提出了各种技术来减轻其影响。 本发明的实施例提供了一种在从时钟处直接测量和去除时钟恢复机制中的PDV效应的机制。 一个具体实施例提供了一种时钟恢复机制,其包括具有内置PDV补偿特征的锁相环(PLL)。 本发明的目的是使从时钟将主时钟恢复到更高的质量,就好像主机和从机之间的通信路径没有PDV一样。 该技术可以允许分组网络提供与时分复用(TDM)网络和全球定位系统(GPS)相同级别的时钟同步服务。

    METHOD AND DEVICES FOR SYNCHRONIZATION USING LINEAR PROGRAMMING
    66.
    发明申请
    METHOD AND DEVICES FOR SYNCHRONIZATION USING LINEAR PROGRAMMING 有权
    使用线性编程进行同步的方法和设备

    公开(公告)号:US20150163000A1

    公开(公告)日:2015-06-11

    申请号:US14100345

    申请日:2013-12-09

    Inventor: James Aweya

    CPC classification number: H04J3/0602 H04J3/0667 H04L7/033

    Abstract: This invention relates to methods and devices for synchronization using linear programming, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a two-dimensional linear programming technique for estimating clock offset and skew, particularly from two-way exchange of timing messages between a master and a slave device. Some embodiments include a skew and offset adjustable free-running counter for regenerating the master time and frequency at the slave device.

    Abstract translation: 本发明涉及使用线性规划进行同步的方法和装置,特别是使用例如IEEE 1588精确时间协议(PTP)的分组网络。 定时协议消息暴露在网络中的伪影,例如分组延迟变化(PDV)或分组丢失。 本发明的实施例提供了一种用于估计时钟偏移和偏移的二维线性规划技术,特别是从主设备和从设备之间的定时消息的双向交换。 一些实施例包括用于在从设备处再生主时间和频率的偏斜和偏移可调自由运行计数器。

    METHOD AND DEVICES FOR TIME AND FREQUENCY SYNCHRONIZATION USING A PHASE LOCKED LOOP
    67.
    发明申请
    METHOD AND DEVICES FOR TIME AND FREQUENCY SYNCHRONIZATION USING A PHASE LOCKED LOOP 有权
    使用相位锁定环路的时间和频率同步的方法和设备

    公开(公告)号:US20150092797A1

    公开(公告)日:2015-04-02

    申请号:US14044075

    申请日:2013-10-02

    Inventor: James Aweya

    CPC classification number: H03L7/1976 H03L2207/50 H04J3/0667 H04J3/0697

    Abstract: This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a digital phase locked loop (DPLL) based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client). An example of this DPLL in conjunction with a recursive least squares mechanism for clock offset and skew estimation is also provided.

    Abstract translation: 本发明涉及用于时间和频率同步的方法和装置,特别是涉及使用例如IEEE 1588精确时间协议(PTP)的分组网络。 定时协议消息暴露在网络中的伪影,例如分组延迟变化(PDV)或分组丢失。 本发明的实施例提供了一种基于直接数字合成的数字锁相环(DPLL),以提供在从机(时间客户机)上使用的时间和频率信号。 还提供了该DPLL与用于时钟偏移和偏移估计的递归最小二乘机制的示例。

    METHOD AND DEVICES FOR SYNCHRONIZATION
    68.
    发明申请
    METHOD AND DEVICES FOR SYNCHRONIZATION 有权
    用于同步的方法和设备

    公开(公告)号:US20150092793A1

    公开(公告)日:2015-04-02

    申请号:US14043068

    申请日:2013-10-01

    Inventor: James Aweya

    CPC classification number: H04J3/0667 H04J3/0685

    Abstract: This invention relates to methods and devices for time and frequency synchronization. The invention has particular application where time and frequency synchronization over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP) is being carried out. The primary challenge in clock distribution over packet networks is the variable transit delays experienced by timing packets, packet delay variations (PDVs). Embodiments of the invention provide a method for time offset alignment with PDV compensation where a synchronized frequency signal is available at a slave device via Synchronous Ethernet and is used to determine the compensation parameters for the PDV.

    Abstract translation: 本发明涉及用于时间和频率同步的方法和装置。 本发明具有特定的应用,其中使用例如IEEE 1588精确时间协议(PTP)的分组网络进行时间和频率同步。 分组网络中时钟分配的主要挑战是定时分组,分组延迟变化(PDV)所经历的可变传输延迟。 本发明的实施例提供了一种用于与PDV补偿的时间偏移对准的方法,其中同步的频率信号在从属设备经由同步以太网可用并且用于确定PDV的补偿参数。

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