公开(公告)号：US11048852B1

公开(公告)日：2021-06-29

申请号：US16523416

申请日：2019-07-26

Applicant: Cadence Design Systems, Inc.

Inventor： Elias Lee Fallon ,  Wangyang Zhang ,  Sheng Qian

IPC: G06F30/30 ,  G06F30/398 ,  G06N20/00 ,  G06F30/20 ,  G06F30/27 ,  G06F30/373 ,  G06F30/337

Abstract: The present disclosure relates to a computer-implemented method for electronic circuit design. Embodiments may include receiving, using at least one processor, data corresponding to an electronic design schematic. Embodiments may further include analyzing the data to learn one or more device size parameters, a range of parameters, or a matching relationship of parameters based upon, at least in part, the electronic design schematic or the electronic design layout, wherein analyzing occurs without user action.

公开(公告)号：US11030378B1

公开(公告)日：2021-06-08

申请号：US16904534

申请日：2020-06-17

Applicant: Cadence Design Systems, Inc.

Inventor： Yi-Xiao Ding ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F30/3947 ,  G06F30/392

Abstract: Various embodiments described herein provide for track assignment of wires of a network of a circuit design by dynamic programming. In particular, various embodiments use a dynamic programming process to determine a set of breaking points for a routing wire of a global-routed and layer-assigned circuit design, and to determine track assignments for each of the sub-wires (sub-routes) formed by applying the set of selected breaking points to the routing wire. This results in a set of track-assigned sub-wires (or track-assigned sub-routes), which various embodiments can connect together to generate a connected set of track-assigned sub-wires that can be used in place of the routing wire.

公开(公告)号：US10996723B1

公开(公告)日：2021-05-04

申请号：US16218079

申请日：2018-12-12

Applicant: Cadence Design Systems, Inc.

Inventor： Quang Nguyen ,  Duc Dang ,  Raju Joshi ,  David Abada ,  Akash Sharma ,  Zhanhe Shi

IPC: G06F1/24 ,  G06F1/10

Abstract: A method for providing, based on an emulation schedule, a reset message to multiple circuits is provided. The reset message associates a reset signal with a selected clock cycle for each circuit, in the emulation schedule. The method includes determining a mask for each of the circuits based on the emulation schedule, providing a clock signal to the circuits, the clock signal comprising the selected clock cycle for each circuit, and tuning the reset signal relative to the clock signal based on a center of the selected clock cycle for each circuit. The method also includes providing the reset signal to the circuits and asserting the reset signal in the circuits based on the mask. A system and a non-transitory, machine-readable medium storing instructions to perform the above method are also provided.

公开(公告)号：US10990733B1

公开(公告)日：2021-04-27

申请号：US16814928

申请日：2020-03-10

Applicant: Cadence Design Systems, Inc.

Inventor： Vibhor Garg ,  Amit Dhuria

IPC: G06F30/3315 ,  G06F119/12

Abstract: According to certain aspects, the present embodiments include techniques for performing a single timing analysis run for a plurality of views representing different modes and/or corners. An embodiment analyzes and maintains relevant timing information that is different for different views, but otherwise maintains the same information for all views. This allows each individual view in a single run to be analyzed in the same manner as separate runs for each separate view, thereby ensuring the same QoR. These and other embodiments provide substantial savings in runtime and memory consumption over other approaches.

公开(公告)号：US10980117B1

公开(公告)日：2021-04-13

申请号：US16218158

申请日：2018-12-12

Applicant: Cadence Design Systems, Inc.

Inventor： Gidon Maas ,  Pinchas Herman ,  Vu Nguyen ,  Hoa Pham ,  Febin George

IPC: H05K1/00 ,  H05K1/14 ,  H03K19/177 ,  H05K5/00 ,  G06F30/34 ,  G06F30/331

Abstract: A mid-plane board including a first connector configured to receive a first signal from a first circuit board is provided. The mid-plane board includes a second connector configured to provide the first signal to a second circuit board. The first circuit board forms a first plane and the second circuit board forms a second plane, and the first plane and the second plane are substantially parallel. The mid-plane board also includes a cutout configured to allow a coplanar connector to bridge the mid-plane board and provide a second signal from the first circuit board to the second circuit board. The second signal is a high-end signal and the first signal is a low-end signal, and the mid-plane board is disposed on a plane substantially orthogonal to the first circuit board and the second circuit board.

公开(公告)号：US10963617B1

公开(公告)日：2021-03-30

申请号：US16735658

申请日：2020-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： Andrew Mark Chapman ,  William Robert Reece ,  Natarajan Viswanathan ,  Mehmet Can Yildiz ,  Gracieli Posser ,  Zhuo Li

IPC: G06F30/00 ,  G06F30/396 ,  G06F30/398 ,  G06F30/20 ,  G06F30/394

Abstract: Aspects of the present disclosure address systems and methods for fixing clock tree design constraint violations. An initial clock tree is generated. The generating of the initial clock tree comprises routing a clock net using an initial value for a parameter that controls a priority ratio between total route length and a maximum source-to-sink route length in each net of the clock tree. A violation to a clock tree design constraint is detected in the clock net in the clock tree, and based on detecting the violation, a rerouting candidate is generated by rerouting the clock net using an adjusted value for the parameter. A target clock tree is selected based on a comparison of timing characteristics of the rerouting candidate with the clock tree design constraint.

公开(公告)号：US10936777B1

公开(公告)日：2021-03-02

申请号：US16777661

申请日：2020-01-30

Applicant: Cadence Design Systems, Inc.

Inventor： Jhih-Rong Gao ,  Yi-Xiao Ding ,  Zhuo Li

IPC: G06F30/00 ,  G06F30/337 ,  G06F30/392 ,  G06F30/31 ,  G06F30/396 ,  G06F30/3312

Abstract: Aspects of the present disclosure address improved systems and methods for rebuffering an integrated circuit (IC) design using a unified improvement scoring algorithm. A plurality of rebuffering candidates are generated based on an initial buffer tree in an integrated circuit (IC) design. A rebuffering candidate in the plurality of rebuffering candidates comprises a modified buffer tree based on the initial buffer tree. A buffering cost of each rebuffering candidate is determined. A reference buffer tree is selected from among the rebuffering candidates based on the buffering cost of each rebuffering candidate. An improvement score of each rebuffering candidate is determined based on the buffering cost of each rebuffering candidate relative to the reference buffer tree. A new buffer tree is selected from among the plurality of rebuffering candidates to replace the initial buffer tree based on the improvement score of each rebuffering candidate.

公开(公告)号：US10902174B1

公开(公告)日：2021-01-26

申请号：US16572377

申请日：2019-09-16

Applicant: Cadence Design Systems, Inc.

Inventor： Xincheng Zhang ,  Jian An ,  Fangfang Li

IPC: G06F30/392 ,  G06F30/394 ,  G06F119/06

Abstract: Various embodiments provide for modeling a power and ground (PG) mesh for a circuit design placement process. For some embodiments, a reference PG mesh can be used to generate a PG mesh model for a circuit design. A PG mesh model can be generated for a circuit design by calculating how much routing resource is occupied by the reference PG mesh of the circuit design, and the resulting PG mesh model can be applied to the circuit design by removing a similar amount of routing resource from the circuit design during a placement circuit design flow. Additionally (or alternatively), a PG mesh model can be generated to comprise a set of metal obstructions that correspond to each macro of the circuit design, and the PG mesh model can be applied to the circuit design by adding the metal obstructions to one or more metal layers of the circuit design.

公开(公告)号：US10860763B1

公开(公告)日：2020-12-08

申请号：US14863788

申请日：2015-09-24

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Yuhei Hayashi

IPC: G06F30/331 ,  G06F9/455

Abstract: Disclosed herein are systems and methods of compiling resources of a programmable emulation system to execute an emulation process, to emulate a logic system, such as an application-specific integrated circuit (ASIC), currently being tested and prototyped, and then revising, transforming, and moving the compiled instructions sets to inexpensively, quickly, and dynamically adapt to unavailable resources, which may be due to previously allocation to a different emulation job, or for fault tolerance. Relocation of the resources that will execute the emulation job (i.e., “footprint”) may refer to the remapping of a compiled footprint to a revised set of resources, defining a revised footprint. Fault tolerance may refer to support for working around faulty hardware components of the emulation system.

公开(公告)号：US10803219B1

公开(公告)日：2020-10-13

申请号：US16361702

申请日：2019-03-22

Applicant: Cadence Design Systems, Inc.

Inventor： Maayan Ziv ,  Hanna Nizar ,  Kanwar Pal Singh ,  Sudeep Kumar Srivastava

IPC: G06F30/33 ,  G06F9/54 ,  G06F30/3323

Abstract: A method for a combined formal static analysis of a design code, the method comprising using a lint checker performing Lint checks to identify a suspected violation in the design code; using a formal static analyzer, performing formal checks to identify a suspected property that corresponds to the suspected violation; applying a formal proof technique to determine whether the suspected property is proven or disproved; and if the suspected property is disproved, issuing an alert.