公开(公告)号：US20140266114A1

公开(公告)日：2014-09-18

申请号：US14291426

申请日：2014-05-30

Applicant: Chan-Hong CHERN ,  Tzu Ching CHANG ,  Min-Shueh YUAN ,  Yuwen SWEI ,  Chih-Chang LIN ,  Chiang PU ,  Ming-Chieh HUANG ,  Kuoyuan HSU

Inventor： Chan-Hong CHERN ,  Tzu Ching CHANG ,  Min-Shueh YUAN ,  Yuwen SWEI ,  Chih-Chang LIN ,  Chiang PU ,  Ming-Chieh HUANG ,  Kuoyuan HSU

IPC: H02M3/158

CPC classification number: H02M3/158 ,  G05F1/44 ,  G05F1/56

Abstract: A voltage regulator circuit comprises an amplifier having an inverting input and a non-inverting input. The amplifier is configured to generate a control signal based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the amplifier. The voltage regulator circuit also comprises an output node, a first power node, a second power node, and a driver that generates a driving current flowing toward the output node in response to the control signal. The driver is coupled between the first power node and the output node. A first transistor having a gate is coupled between the output node and the second power node. A bias circuit outside the amplifier supplies a bias signal to the gate of the first transistor, which is configured to operate in a saturation mode based on the bias signal supplied by the bias circuit.

Abstract translation: 电压调节器电路包括具有反相输入和非反相输入的放大器。 放大器被配置为基于放大器的反相输入端处的参考信号和放大器的非反相输入端的反馈信号产生控制信号。 电压调节器电路还包括响应于控制信号产生朝向输出节点流动的驱动电流的输出节点，第一功率节点，第二功率节点和驱动器。 驱动器耦合在第一功率节点和输出节点之间。 具有栅极的第一晶体管耦合在输出节点和第二功率节点之间。 放大器外部的偏置电路向第一晶体管的栅极提供偏置信号，该偏置信号被配置为基于偏置电路提供的偏置信号在饱和模式下工作。

公开(公告)号：US08661389B2

公开(公告)日：2014-02-25

申请号：US13084748

申请日：2011-04-12

Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh ,  Li-Chun Tien

Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Li-Chun Tien

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method of designing an integrated circuit includes providing a cell library including a first and second cell structures. The cell structures each include a dummy gate electrode disposed on a boundary. An edge gate electrode is disposed adjacent to the dummy gate electrode. An oxide definition (OD) region has an edge disposed between the edge gate electrode and the dummy gate electrode. The method includes determining if the cell structures are to be abutted with each other. If so, the method includes abutting the cell structures. If not so, the method includes increasing areas of portions of the OD regions between the edge gate electrodes and the dummy gate electrodes.

Abstract translation: 设计集成电路的方法包括提供包括第一和第二单元结构的单元库。 电池结构各自包括设置在边界上的虚拟栅电极。 边缘栅电极被设置成与虚拟栅电极相邻。 氧化物定义（OD）区域具有设置在边缘栅电极和伪栅电极之间的边缘。 该方法包括确定单元结构是否彼此邻接。 如果是，则该方法包括邻接单元结构。 如果不是这样，则该方法包括增加边缘栅极电极和虚拟栅电极之间的OD区域的部分区域。

公开(公告)号：US20140015582A1

公开(公告)日：2014-01-16

申请号：US13547396

申请日：2012-07-12

Applicant: Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Tsung-Ching HUANG ,  Derek C. TAO

Inventor： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Tsung-Ching HUANG ,  Derek C. TAO

IPC: H03K3/356

CPC classification number: H03K5/08 ,  H03K3/356139 ,  H04L27/01

Abstract: This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal.

Abstract translation: 该描述涉及包括第一锁存器的限幅器。 第一锁存器包括被配置为接收第一时钟信号的评估晶体管和被配置为接收第二时钟信号的显影晶体管。 第一时钟信号与第二时钟信号不同。 第一锁存器包括被配置为接收第一和第二互补输入的第一和第二输入晶体管。 第一锁存器包括配置成接收第三时钟信号的至少一个预充电晶体管。 第一锁存器还包括至少一个交叉锁存晶体管对，该至少一个交叉锁存晶体管对连接在评估晶体管与第一和第二输出节点之间。 切片器包括连接到第一和第二输出节点和第三输出节点的第二锁存器。 切片器包括连接到第三输出节点并被配置为产生最终输出信号的缓冲器。

公开(公告)号：US20130346811A1

公开(公告)日：2013-12-26

申请号：US13528877

申请日：2012-06-21

Applicant: Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Yuwen SWEI ,  Chih-Chang LIN ,  Tsung-Ching HUANG

Inventor： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Yuwen SWEI ,  Chih-Chang LIN ,  Tsung-Ching HUANG

IPC: G06F1/04 ,  G06F11/00

CPC classification number: H04L25/03057 ,  H04L25/06 ,  H04L25/08

Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

Abstract translation: 电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。 求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。 第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号 由第一求和电路接收。 第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号 由第一求和电路接收。

公开(公告)号：US20130141170A1

公开(公告)日：2013-06-06

申请号：US13312228

申请日：2011-12-06

Applicant: Tao Wen CHUNG ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Yuwen SWEI

Inventor： Tao Wen CHUNG ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Yuwen SWEI

IPC: H03F3/68

CPC classification number: H03F3/68 ,  H03F1/42 ,  H03F3/191 ,  H03F3/195 ,  H03F3/45183 ,  H03F2200/36 ,  H03F2200/405 ,  H03F2203/45638 ,  H03F2203/45702

Abstract: A method of sharing inductors for inductive peaking of an amplifier having at least two stages includes calculating a single stage inductance of a single stage of the at least two stages for inductive peaking in order to have a stable impulse response. A shared inductance is calculated for inductive peaking by dividing the single stage inductance by a number of stages of the at least two stages. At least two inductors having the shared inductance are shared among the at least two stages for inductive peaking.

Abstract translation: 共享用于具有至少两级的放大器的感应峰化的电感器的方法包括计算用于感应峰值的至少两级的单级的单级电感，以便具有稳定的脉冲响应。 通过将单级电感除以至少两级的多个级来计算感应峰值的共享电感。 具有共享电感的至少两个电感器在用于感应峰化的至少两个级中共享。

公开(公告)号：US08378756B2

公开(公告)日：2013-02-19

申请号：US12782064

申请日：2010-05-18

Applicant: Ming-Chieh Huang ,  Chiang Pu ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei

Inventor： Ming-Chieh Huang ,  Chiang Pu ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei

IPC: H03B5/30 ,  G01C19/00

CPC classification number: H03B5/30

Abstract: Some embodiments regard a method comprising: generating a current according to a movement of the MEMS device; the movement is controlled by a control signal; generating a peak voltage according to the current; and adjusting the control signal when the peak voltage is out of a predetermined range.

Abstract translation: 一些实施例涉及一种方法，包括：根据MEMS装置的移动产生电流; 移动由控制信号控制; 根据电流产生峰值电压; 以及当峰值电压超出预定范围时调节控制信号。

公开(公告)号：US08354862B2

公开(公告)日：2013-01-15

申请号：US13448878

申请日：2012-04-17

Applicant: Chih-Chang Lin ,  Chan-Hong Chern ,  Steven Swei ,  Ming-Chieh Huang ,  Tien-Chun Yang

Inventor： Chih-Chang Lin ,  Chan-Hong Chern ,  Steven Swei ,  Ming-Chieh Huang ,  Tien-Chun Yang

IPC: H03D13/00

CPC classification number: H03L7/08 ,  H03L7/081 ,  H03L7/087

Abstract: A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.

Abstract translation: 包括被配置为接收输入信号和时钟的第一，第三和第五相位时钟并且产生指示时钟的第一早期信号的第一电路的电路早于输入信号，并且指示时钟的第一晚信号晚于 输入信号。 电路还包括配置成接收时钟的输入信号和第二，第四和第六相位时钟的第二电路，并且产生指示时钟早于输入信号的第二早期信号，并且指示时钟的第二延迟信号是 晚于输入信号。 电路还包括被配置为产生第一增加信号的第三电路。 电路还包括被配置为产生第一减小信号的第四电路。

公开(公告)号：US08321828B2

公开(公告)日：2012-11-27

申请号：US12684819

申请日：2010-01-08

Applicant: Chan-Hong Chern

Inventor： Chan-Hong Chern

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0692

Abstract: A method of forming an integrated circuit structure on a chip includes extracting an active layer from a design of the integrated circuit structure, forming a guard band conforming to the shape of the active layer, the guard band surrounds the active layer, and the guard band is spaced from the active layer at a first spacing in the X-axis direction and at a second spacing in the Y-axis direction, removing any part of the guard band that violates design rules, removing convex corners of the guard band, and adding dummy diffusion patterns into the remaining space of the chip outside the guard band. The first and second spacing can be specified as the same spacings in a Spice model characterization of the integrated circuit structure. The dummy diffusion patterns with different granularities can be added so that the diffusion density is substantially uniform over the chip.

Abstract translation: 在芯片上形成集成电路结构的方法包括从集成电路结构的设计中提取有源层，形成符合有源层形状的保护带，保护带围绕有源层，保护带 与有源层以X轴方向的第一间隔和Y轴方向上的第二间隔与有源层间隔开，去除违反设计规则的保护带的任何部分，去除保护带的凸角，并添加 伪散射图案进入保护带外部芯片的剩余空间。 在集成电路结构的Spice模型表征中，第一和第二间隔可以被指定为相同的间距。 可以添加具有不同粒度的虚拟扩散图案，使得扩散密度在芯片上基本均匀。

公开(公告)号：US20120223752A1

公开(公告)日：2012-09-06

申请号：US13039095

申请日：2011-03-02

Applicant: Ming-Chieh HUANG ,  Chih-Chang LIN ,  Tao Wen CHUNG ,  Chan-Hong CHERN

Inventor： Ming-Chieh HUANG ,  Chih-Chang LIN ,  Tao Wen CHUNG ,  Chan-Hong CHERN

IPC: H03L7/06

CPC classification number: H03L7/0896 ,  H03L7/089 ,  H03L7/0893

Abstract: A phase locked loop (PLL) includes a voltage controlled oscillator (VCO) configured to supply an output signal. A phase frequency detector (PFD) is configured to receive a reference frequency signal and to provide a first control signal. A first charge pump is configured to receive the first control signal and to provide a first voltage signal in order to control the VCO. A second charge pump is configured to receive the first control signal and to provide a second voltage signal. A comparator is configured to receive a reference voltage signal, to compare the reference voltage signal and the second voltage signal, and to provide a second control signal. The PFD is configured to adjust at least one side slope of the first control signal based on the second control signal.

Abstract translation: 锁相环（PLL）包括配置成提供输出信号的压控振荡器（VCO）。 相位频率检测器（PFD）被配置为接收参考频率信号并提供第一控制信号。 第一电荷泵被配置为接收第一控制信号并提供第一电压信号以便控制VCO。 第二电荷泵被配置为接收第一控制信号并提供第二电压信号。 比较器被配置为接收参考电压信号，以比较参考电压信号和第二电压信号，并提供第二控制信号。 PFD被配置为基于第二控制信号来调整第一控制信号的至少一个侧斜率。

公开(公告)号：US20120200323A1

公开(公告)日：2012-08-09

申请号：US13448878

申请日：2012-04-17

Applicant: Chih-Chang LIN ,  Chan-Hong CHERN ,  Steven SWEI ,  Ming-Chieh HUANG ,  Tien-Chun YANG

Inventor： Chih-Chang LIN ,  Chan-Hong CHERN ,  Steven SWEI ,  Ming-Chieh HUANG ,  Tien-Chun YANG

IPC: H03L7/06

CPC classification number: H03L7/08 ,  H03L7/081 ,  H03L7/087

Abstract: A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.

Abstract translation: 包括被配置为接收输入信号和时钟的第一，第三和第五相位时钟并且产生指示时钟的第一早期信号的第一电路的电路早于输入信号，并且指示时钟的第一晚信号晚于 输入信号。 电路还包括配置成接收时钟的输入信号和第二，第四和第六相位时钟的第二电路，并且产生指示时钟早于输入信号的第二早期信号，并且指示时钟的第二延迟信号是 晚于输入信号。 电路还包括被配置为产生第一增加信号的第三电路。 电路还包括被配置为产生第一减小信号的第四电路。