公开(公告)号：US20090102018A1

公开(公告)日：2009-04-23

申请号：US12276152

申请日：2008-11-21

Applicant: Donald L. Yates ,  Garry A. Mercaldi

Inventor： Donald L. Yates ,  Garry A. Mercaldi

IPC: H01L29/92

CPC classification number: H01L28/92 ,  G03F7/0035 ,  G03F7/201 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0275 ,  H01L21/32139 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract translation: 用于集成电路的容器结构及其制造方法，而不使用机械平面化（例如化学机械平面化（CMP）），从而消除了CMP引起的缺陷和变化。 该方法利用在非机械去除暴露的表面层期间的孔的局部掩蔽来保护孔的内部。 通过将抗蚀剂层与电磁或热能的差分曝光来实现局部掩蔽。 容器结构适用于并入这种存储单元的存储器单元和装置以及其它集成电路。

公开(公告)号：US20080283796A1

公开(公告)日：2008-11-20

申请号：US12168475

申请日：2008-07-07

Applicant: Donald L. Yates

Inventor： Donald L. Yates

IPC: C09K13/06

CPC classification number: C09K13/08 ,  B08B3/08 ,  C09K13/00 ,  C09K13/04 ,  C09K13/06 ,  C11D7/08 ,  C11D7/10 ,  C11D7/50 ,  C11D11/0047 ,  C23G1/02 ,  G03F7/423 ,  H01L21/31111 ,  H01L21/31133 ,  Y10S438/948

Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute. The composition can also be formulated to selectively remove a photoresist layer, leaving the underlying low-k dielectric layer essentially intact.

Abstract translation: 提供了用于清洁半导体晶片的表面的改进的组合物和方法。 该组合物可用于选择性地除去低k介电材料，例如二氧化硅，覆盖低k电介质层的光致抗蚀剂层，或从晶片表面两层。 根据本发明配制组合物以从晶片的表面提供低k电介质和/或光致抗蚀剂的期望的去除速率。 通过改变氟离子成分以及氟离子成分和酸，成分和控制pH的量，可以配制组合物以实现期望的低k电介质去除速率，其范围从慢和约在约 每分钟50至约1000埃，以每分钟大约1000埃的速度相对快速地除去低k电介质材料。 组合物也可以配制成选择性地除去光致抗蚀剂层，使底层的低k电介质层基本上完整无缺。

公开(公告)号：US07432214B2

公开(公告)日：2008-10-07

申请号：US10889280

申请日：2004-07-12

Applicant: Donald L Yates

Inventor： Donald L Yates

IPC: H01L21/302

CPC classification number: C09K13/08 ,  B08B3/08 ,  C09K13/00 ,  C09K13/04 ,  C09K13/06 ,  C11D7/08 ,  C11D7/10 ,  C11D7/50 ,  C11D11/0047 ,  C23G1/02 ,  G03F7/423 ,  H01L21/31111 ,  H01L21/31133 ,  Y10S438/948

Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute. The composition can also be formulated to selectively remove a photoresist layer, leaving the underlying low-k dielectric layer essentially intact.

公开(公告)号：US07402879B2

公开(公告)日：2008-07-22

申请号：US11134321

申请日：2005-05-23

Applicant: Donald L. Yates ,  Joel A. Drewes

Inventor： Donald L. Yates ,  Joel A. Drewes

IPC: H01L29/82

CPC classification number: H01L27/222 ,  G11C11/15 ,  H01L21/7684

Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.

Abstract translation: 本发明提供了一种制造存储单元的一部分的方法，该方法包括提供一沟槽中的第一导体，其设置在绝缘层中并使绝缘层和第一导体的上表面平坦化，形成材料层 在绝缘层和第一导体的平坦的上表面上方，并且使材料层的上部平坦化，同时在绝缘层和第一导体上完整地保留材料层的下部。

公开(公告)号：US07384727B2

公开(公告)日：2008-06-10

申请号：US10609311

申请日：2003-06-26

Applicant: Donald L. Yates

Inventor： Donald L. Yates

IPC: G03F7/26

CPC classification number: H01L21/0274 ,  G03F7/095 ,  H01L21/3085

Abstract: The invention includes semiconductor processing patterning methods and semiconductor constructions. A semiconductor processing patterning method includes forming a second composition resist layer over a different first composition resist layer. Overlapping portions of the first and second composition resist layers are exposed to actinic energy effective to change solubility of the exposed portions versus the unexposed portions of each of the first and second composition resist layers in a developer solution. The first and second composition resist layers are developed with the developer solution under conditions effective to remove the exposed portions of the first composition resist layer at a faster rate than removing the exposed portions of the second composition resist layer. Additional aspects and implementations are contemplated.

Abstract translation: 本发明包括半导体处理图案化方法和半导体结构。 半导体处理图案化方法包括在不同的第一组合物抗蚀剂层上形成第二组合物抗蚀剂层。 第一和第二组合物抗蚀剂层的重叠部分暴露于有效地改变曝光部分相对于显影剂溶液中第一和第二组合物抗蚀剂层中的每一个的未曝光部分的溶解度的光化能。 第一和第二组合物抗蚀剂层与显影剂溶液一起显影，条件是有效地以比除去第二组合物抗蚀剂层的暴露部分更快的速度除去第一组合物抗蚀剂层的曝光部分。 考虑另外的方面和实现。

公开(公告)号：US07375388B2

公开(公告)日：2008-05-20

申请号：US10734201

申请日：2003-12-15

Applicant: Donald L. Yates ,  Joel A. Drewes

Inventor： Donald L. Yates ,  Joel A. Drewes

IPC: H01L29/76

CPC classification number: H01L27/222 ,  G11C11/15 ,  H01L21/7684

Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.

Abstract translation: 本发明提供了一种制造存储单元的一部分的方法，该方法包括提供一沟槽中的第一导体，其设置在绝缘层中并使绝缘层和第一导体的上表面平坦化，形成材料层 在绝缘层和第一导体的平坦的上表面上方，并且使材料层的上部平坦化，同时在绝缘层和第一导体上完整地保留材料层的下部。

公开(公告)号：US07261835B2

公开(公告)日：2007-08-28

申请号：US10338845

申请日：2003-01-09

Applicant: Kevin J. Torek ,  Donald L. Yates

Inventor： Kevin J. Torek ,  Donald L. Yates

IPC: C09K13/00

CPC classification number: H01L21/31116 ,  C09K13/08 ,  C11D7/08 ,  C11D7/265 ,  C11D11/0047 ,  H01L21/02063 ,  H01L21/31144

Abstract: A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of phosphoric acid, hydrofluoric acid, and a carboxylic acid, such as acetic acid, which removes the remaining dry etch residues while minimizing removal of material from desired substrate features. The approximate proportions of the conditioning solution are typically 80 to 95 percent acetic acid, 1 to 15 percent phosphoric acid, and 0.01 to 5.0 percent hydrofluoric acid.

Abstract translation: 从半导体衬底干法蚀刻工艺后残留的有机金属和有机硅酸盐残渣的方法。 将基底暴露于磷酸，氢氟酸和羧酸（例如乙酸）的调理溶液中，其除去剩余的干蚀刻残留物，同时最小化从所需底物特征中去除材料。 调理溶液的大致比例通常为80至95％的乙酸，1至15％的磷酸和0.01至5.0％的氢氟酸。

公开(公告)号：US07018937B2

公开(公告)日：2006-03-28

申请号：US10231416

申请日：2002-08-29

Applicant: Donald L. Yates

Inventor： Donald L. Yates

IPC: H01L21/302

CPC classification number: H01L21/02071 ,  H01L21/02052 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/32136 ,  H01L43/12

Abstract: A composition and methods for using the composition in removing processing byproducts is provided. The composition can be non-aqueous or semi-aqueous. The non-aqueous composition includes a non-aqueous solvent and one or more components including a fluoride compound and a pyridine compound. The semi-aqueous composition includes glacial acetic acid and one or more components including a fluoride compound and a pyridine compound. The composition can be used in removing processing byproducts from substrate assembly, including MRAM devices, that include at least a metal containing region and processing byproducts, where removing the processing byproducts includes exposing the substrate assembly to the composition for a time effective to remove at least a portion of the processing byproducts.

公开(公告)号：US06762132B1

公开(公告)日：2004-07-13

申请号：US09652991

申请日：2000-08-31

Applicant: Donald L. Yates

Inventor： Donald L. Yates

IPC: H01L21302

CPC classification number: C09K13/08 ,  B08B3/08 ,  C09K13/00 ,  C09K13/04 ,  C09K13/06 ,  C11D7/08 ,  C11D7/10 ,  C11D7/50 ,  C11D11/0047 ,  C23G1/02 ,  G03F7/423 ,  H01L21/31111 ,  H01L21/31133 ,  Y10S438/948

Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute. The composition can also be formulated to selectively remove a photoresist layer, leaving the underlying low-k dielectric layer essentially intact.

Abstract translation: 提供了用于清洁半导体晶片的表面的改进的组合物和方法。 该组合物可用于选择性地除去低k介电材料，例如二氧化硅，覆盖低k电介质层的光致抗蚀剂层，或从晶片表面两层。 根据本发明配制组合物以从晶片的表面提供低k电介质和/或光致抗蚀剂的期望的去除速率。 通过改变氟离子成分以及氟离子成分和酸，成分和控制pH的量，可以配制组合物以实现期望的低k电介质去除速率，其范围从慢和约在约 每分钟50至约1000埃，以每分钟大约1000埃的速度相对快速地除去低k电介质材料。 组合物也可以配制成选择性地除去光致抗蚀剂层，使底层的低k电介质层基本上完整无缺。

公开(公告)号：US06607001B1

公开(公告)日：2003-08-19

申请号：US09427789

申请日：1999-10-27

Applicant: Donald L. Yates

Inventor： Donald L. Yates

IPC: B08B304

CPC classification number: H01L21/67034 ,  H01L21/02052 ,  H01L21/02057 ,  H01L21/67028 ,  H01L21/67057 ,  Y10S134/902

Abstract: The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel.