公开(公告)号：US20100002510A1

公开(公告)日：2010-01-07

申请号：US12560503

申请日：2009-09-16

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621 ,  G11C2211/5641

Abstract: A NAND type flash memory includes first to third memory cell transistors having current paths connected in series between one end of a current path of each of first and second selection transistors, and each having a control gate and a charge storage layer, the first and second memory cell transistors being adjacent to the first and second selection transistors, the third memory cell transistor being positioned between the first and second memory cell transistors, the third memory cell transistor holding data having not less than three bits, the first memory cell transistor holding 2-bit data in which middle and upper pages is written by skipping a lower page, and a lower page verify voltage being set when writing the middle page, and a middle page verify voltage is set when writing the upper page, changing a position of a threshold distribution of the first memory cell transistor.

Abstract translation: NAND型闪存包括第一至第三存储单元晶体管，其具有串联连接在第一和第二选择晶体管中的每一个的电流路径的一端之间的电流路径，并且每个存储单元晶体管具有控制栅极和电荷存储层，第一和第二 存储单元晶体管与第一和第二选择晶体管相邻，第三存储单元晶体管位于第一和第二存储单元晶体管之间，第三存储单元晶体管保持具有不少于3位的数据，第一存储单元晶体管保持2 通过跳过下页来写入中间页和上页的位数数据，以及写入中间页时设置的下页验证电压，并且在写入上页时设置中间页验证电压，改变位置 第一存储单元晶体管的阈值分布。

公开(公告)号：US20090292863A1

公开(公告)日：2009-11-26

申请号：US12405754

申请日：2009-03-17

Applicant: Hitoshi Shiga ,  Hidetaka Tsuji

Inventor： Hitoshi Shiga ,  Hidetaka Tsuji

IPC: G06F12/02 ,  G06F12/00

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: A memory system with a semiconductor memory device, in which a physical block of n-bits serves as an erase unit, wherein the address management of the memory device is performed by a logical block with m-bits, “m” being larger than “n” and expressed by a power of two, and wherein a n-bit portion continued from the head address in the logical block is defined as a first management unit corresponding to one physical block of the memory device, and a number of the remaining fraction portions each defined as a second management unit are gathered so as to correspond to one physical block of the memory device.

Abstract translation: 一种具有半导体存储器件的存储器系统，其中n位的物理块用作擦除单元，其中存储器件的地址管理由具有m位的逻辑块执行，“m”大于“ n“并且由2的幂表示，并且其中从逻辑块中的头地址继续的n位部分被定义为与存储器件的一个物理块相对应的第一管理单元，并且剩余部分的数量 收集每个被定义为第二管理单元的部分，以对应于存储器件的一个物理块。

公开(公告)号：US07619920B2

公开(公告)日：2009-11-17

申请号：US11773771

申请日：2007-07-05

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621 ,  G11C2211/5641

Abstract: A NAND type flash memory includes first to third memory cell transistors having current paths connected in series between one end of a current path of each of first and second selection transistors, and each having a control gate and a charge storage layer, the first and second memory cell transistors being adjacent to the first and second selection transistors, the third memory cell transistor being positioned between the first and second memory cell transistors, the third memory cell transistor holding data having not less than three bits, the first memory cell transistor holding 2-bit data in which middle and upper pages is written by skipping a lower page, and a lower page verify voltage being set when writing the middle page, and a middle page verify voltage is set when writing the upper page, changing a position of a threshold distribution of the first memory cell transistor.

Abstract translation: NAND型闪存包括第一至第三存储单元晶体管，其具有串联连接在第一和第二选择晶体管中的每一个的电流路径的一端之间的电流路径，并且每个存储单元晶体管具有控制栅极和电荷存储层，第一和第二 存储单元晶体管与第一和第二选择晶体管相邻，第三存储单元晶体管位于第一和第二存储单元晶体管之间，第三存储单元晶体管保持具有不少于3位的数据，第一存储单元晶体管保持2 通过跳过下页来写入中间页和上页的位数数据，以及写入中间页时设置的下页验证电压，并且在写入上页时设置中间页验证电压，改变位置 第一存储单元晶体管的阈值分布。

公开(公告)号：US20090010063A1

公开(公告)日：2009-01-08

申请号：US11773771

申请日：2007-07-05

Applicant: Hitoshi SHIGA

Inventor： Hitoshi SHIGA

IPC: G11C11/34 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621 ,  G11C2211/5641

Abstract: A NAND type flash memory includes first to third memory cell transistors having current paths connected in series between one end of a current path of each of first and second selection transistors, and each having a control gate and a charge storage layer, the first and second memory cell transistors being adjacent to the first and second selection transistors, the third memory cell transistor being positioned between the first and second memory cell transistors, the third memory cell transistor holding data having not less than three bits, the first memory cell transistor holding 2-bit data in which middle and upper pages is written by skipping a lower page, and a lower page verify voltage being set when writing the middle page, and a middle page verify voltage is set when writing the upper page, changing a position of a threshold distribution of the first memory cell transistor.

Abstract translation: NAND型闪存包括第一至第三存储单元晶体管，其具有串联连接在第一和第二选择晶体管中的每一个的电流路径的一端之间的电流路径，并且每个存储单元晶体管具有控制栅极和电荷存储层，第一和第二 存储单元晶体管与第一和第二选择晶体管相邻，第三存储单元晶体管位于第一和第二存储单元晶体管之间，第三存储单元晶体管保持具有不少于3位的数据，第一存储单元晶体管保持2 通过跳过下页来写入中间页和上页的位数数据，以及写入中间页时设置的下页验证电压，并且在写入上页时设置中间页验证电压，改变位置 第一存储单元晶体管的阈值分布。

公开(公告)号：US20080239805A1

公开(公告)日：2008-10-02

申请号：US11863915

申请日：2007-09-28

Applicant: Hitoshi SHIGA ,  Susumu Fujimura ,  Yoshihiko Shindo

Inventor： Hitoshi SHIGA ,  Susumu Fujimura ,  Yoshihiko Shindo

IPC: G11C16/06

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5646

Abstract: A nonvolatile semiconductor memory according to the present invention includes a memory cell array including a plurality of electrically writable memory cells; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells; and a data reading and programming control section for, when performing 4-value data programming, read or erasure with respect to at least one of the plurality of memory cells, selecting and applying a voltage to a corresponding word line and a corresponding bit line among the plurality of word lines and the plurality of bit lines; wherein the data reading and programming control section includes an adjacent memory cell data reading section for reading, at a reading voltage of a predetermined reading voltage level, whether or not data is programmed in a lower page of a second memory cell adjacent to a first memory cell in the memory cell array, and generating adjacent memory cell state data which represents a data state of the second memory cell; an adjacent memory cell data memory section for storing the adjacent memory cell state data generated by the adjacent memory cell data reading section; a reading voltage level control section for defining a plurality of predetermined reading voltage verify levels for reading data from the first memory cell based on the adjacent memory cell state data; a data reading section for reading the data from the first memory cell at a plurality of reading voltages corresponding to the plurality of predetermined reading voltage verify levels; and a data determining section for determining which data of 4-value data is programmed in the first memory cell based on the data which is read by the data reading section.

Abstract translation: 根据本发明的非易失性半导体存储器包括：包括多个电可写存储单元的存储单元阵列; 连接到所述多个存储单元的多个字线和多个位线; 以及数据读取和编程控制部分，用于当对所述多个存储器单元中的至少一个进行4值数据编程时，读取或擦除所述多个存储器单元中的至少一个，选择并施加电压到相应的字线和相应的位线之间 所述多个字线和所述多个位线; 其中所述数据读取和编程控制部分包括相邻存储单元数据读取部分，用于在预定读取电压电平的读取电压下读取与第一存储器相邻的第二存储器单元的下部页面中的数据是否被编程 并且生成表示第二存储单元的数据状态的相邻存储单元状态数据; 相邻的存储单元数据存储部，用于存储由相邻存储单元数据读取部生成的相邻的存储单元状态数据; 读取电压电平控制部分，用于基于相邻的存储器单元状态数据定义用于从第一存储器单元读取数据的多个预定读取电压验证电平; 数据读取部分，用于以对应于多个预定读取电压验证电平的多个读取电压读取来自第一存储器单元的数据; 以及数据确定部分，用于基于由数据读取部分读取的数据确定在第一存储器单元中哪个数据被编程。

公开(公告)号：US07382652B2

公开(公告)日：2008-06-03

申请号：US11564887

申请日：2006-11-30

Applicant: Hitoshi Shiga ,  Chih-Hung Wang ,  Chin Hsi Lin

Inventor： Hitoshi Shiga ,  Chih-Hung Wang ,  Chin Hsi Lin

IPC: G11C16/04

CPC classification number: G11C16/344 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/16 ,  G11C2211/5621

Abstract: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.

Abstract translation: 半导体存储器件包括存储单元阵列，数据缓冲器和列开关。 数据缓冲器检测位线的电位以确定所选择的存储单元中的数据并保持读取中的读出数据。 数据缓冲器检测整个数据缓冲器是否保持“0”数据以及整个数据缓冲器是否保持“1”数据。 列开关选择数据缓冲区的一部分，并将部件连接到总线。

公开(公告)号：US20060087887A1

公开(公告)日：2006-04-27

申请号：US11235206

申请日：2005-09-27

Applicant: Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawal

Inventor： Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawal

IPC: G11C16/06

CPC classification number: G11C16/102

Abstract: The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.

Abstract translation: 非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。 当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持 电路工作。 然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。 同时，将数据输出到奇数位线，并且确定奇数位线的电位。 然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。

公开(公告)号：US20050146959A1

公开(公告)日：2005-07-07

申请号：US10856851

申请日：2004-06-01

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G01R31/28 ,  G06F11/10 ,  G11C7/00 ,  G11C16/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/26 ,  G11C16/34 ,  G11C29/00 ,  G11C29/12

CPC classification number: G11C16/26 ,  G06F11/1068 ,  G11C16/0483 ,  G11C16/3418

Abstract: A non-volatile semiconductor memory device includes: a cell array having electrically rewritable and non-volatile memory cells arranged therein; and a sense amplifier circuit configured to detect voltage change of a bit line in the cell array, thereby reading data of a selected memory cell coupled to the bit line, wherein the sense amplifier circuit is controlled to read data at plural timings within a period in which the bit line voltage is changing in correspondence with the selected memory cell, and compare data read out by successive two data read operations with each other so as to judge a threshold margin of the selected memory cell.

Abstract translation: 非易失性半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的单元阵列; 以及读出放大器电路，被配置为检测所述单元阵列中的位线的电压变化，从而读取耦合到所述位线的所选存储单元的数据，其中所述读出放大器电路被控制为在多个定时内在 位线电压与所选择的存储单元相对应地变化，并且通过连续两个数据读取操作读出的数据彼此进行比较，以便判断所选存储单元的阈值余量。

公开(公告)号：US06888764B2

公开(公告)日：2005-05-03

申请号：US10231283

申请日：2002-08-30

Applicant: Hitoshi Shiga ,  Tadayuki Taura ,  Shigeru Atsumi

Inventor： Hitoshi Shiga ,  Tadayuki Taura ,  Shigeru Atsumi

IPC: G01R31/28 ,  G11C16/02 ,  G11C16/06 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  G11C29/10 ,  G11C29/12 ,  G11C7/00

CPC classification number: G11C29/76 ,  G11C16/04 ,  G11C2029/1802

Abstract: A semiconductor device has an address counter to output, in a first mode, a first block address whereas, in a second mode, a second block address selected from a block-address space two times larger than a block-address space corresponding to memory blocks, the memory blocks and at least one redundant block being included in a memory section, and a block-selection controller, in the second mode, one of the memory blocks, which corresponds to the output of the address counter, when the most significant value of the second block address as the output of the address counter is at a first level whereas select the redundant block while the memory blocks are inhibited from selection, when the most significant value is at a second level.

Abstract translation: 半导体器件具有地址计数器，以第一模式输出第一块地址，而在第二模式中，从与存储块对应的块地址空间大2倍的块地址空间中选择第二块地址 存储器块和至少一个冗余块被包括在存储器部分中，以及块选择控制器，在第二模式中，当最大有效值时对应于地址计数器的输出的存储块之一 作为地址计数器的输出的第二块地址处于第一级，而当最高有效值处于第二级时，选择该冗余块而存储块被禁止选择。

公开(公告)号：US06778443B2

公开(公告)日：2004-08-17

申请号：US10328149

申请日：2002-12-23

Applicant: Hitoshi Shiga ,  Tokumasa Hara ,  Tadayuki Taura

Inventor： Hitoshi Shiga ,  Tokumasa Hara ,  Tadayuki Taura

IPC: G11C1604

CPC classification number: G11C16/107 ,  G11C16/16 ,  G11C16/344 ,  G11C16/3445

Abstract: A non-volatile semiconductor memory device comprises a plurality of blocks each having a plurality of memory cells to be erased at a time and a decoder for selecting the memory cells, each of the blocks having a block decoder for latching a selection signal thereof in pre-programming and for selecting all of the latched blocks by the selection signal at the same time, a sense amplifier, and an address control circuit for controlling a sequence, the sequence including counting addresses of the memory cells in erasing and erasing all of the selected memory cells after pre-programming, all of the blocks having the latched selection signal being controlled to be collectively erased by the address control circuit.

Abstract translation: 一种非易失性半导体存储器件包括多个块，每个块具有一次要擦除的多个存储器单元和用于选择存储器单元的解码器，每个块具有块解码器，用于将其选择信号锁存在预先 编程并用于同时通过选择信号选择所有锁存块，读出放大器和用于控制序列的地址控制电路，该序列包括擦除和擦除所有所选择的所有存储单元的计数地址 预编程后的存储单元，具有锁存选择信号的所有块被控制为由地址控制电路共同擦除。