公开(公告)号：US20120038045A1

公开(公告)日：2012-02-16

申请号：US13110433

申请日：2011-05-18

Applicant: Ho-Cheol Lee

Inventor： Ho-Cheol Lee

IPC: H01L23/498 ,  H01L23/48 ,  H01L21/50

CPC classification number: H01L24/97 ,  H01L23/3107 ,  H01L23/481 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00

Abstract: A stacked semiconductor device may have a plurality of chips stacked in three-dimension. The stacked semiconductor device may include a first semiconductor chip and at least one second semiconductor chip. The first semiconductor chip may include a plurality of first through silicon vias (TSVs). The at least one second semiconductor chip may include a plurality of second TSVs. The at least one second semiconductor chip may be stacked above the first semiconductor chip and may be thinner than the first semiconductor chip. Therefore, the stacked semiconductor device may have an improved reliability.

Abstract translation: 叠层半导体器件可以具有三维堆叠的多个芯片。 层叠的半导体器件可以包括第一半导体芯片和至少一个第二半导体芯片。 第一半导体芯片可以包括多个第一至第二通孔（TSV）。 所述至少一个第二半导体芯片可以包括多个第二TSV。 所述至少一个第二半导体芯片可以堆叠在第一半导体芯片之上并且可以比第一半导体芯片更薄。 因此，堆叠式半导体器件可以具有改善的可靠性。

公开(公告)号：USD645491S1

公开(公告)日：2011-09-20

申请号：US29365838

申请日：2010-07-15

Applicant: Ho Cheol Lee

Designer： Ho Cheol Lee

公开(公告)号：USD637576S1

公开(公告)日：2011-05-10

申请号：US29365857

申请日：2010-07-15

Applicant: Ho Cheol Lee

Designer： Ho Cheol Lee

公开(公告)号：US07941612B2

公开(公告)日：2011-05-10

申请号：US11829859

申请日：2007-07-27

Applicant: Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Dong-Hyuk Lee ,  Jong-Wook Park ,  Ho-Cheol Lee ,  Mi-Jo Kim ,  Jung-Sik Kim ,  Chang-Ho Lee

Inventor： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Dong-Hyuk Lee ,  Jong-Wook Park ,  Ho-Cheol Lee ,  Mi-Jo Kim ,  Jung-Sik Kim ,  Chang-Ho Lee

IPC: G06F12/00

CPC classification number: G11C7/1075 ,  G11C7/1012 ,  G11C11/4096

Abstract: A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.

Abstract translation: 多路可及半导体存储器件提供处理器之间的接口功能。 存储器设备可以包括具有可操作地耦合到两个或更多个端口的共享存储器区域的存储单元阵列，该两个或多个端口可由两个或多个处理器独立地访问;访问路径形成单元，用于在一个端口和共享之间形成数据访问路径 响应于由处理器施加的外部信号的存储区域以及具有信号量区域和由两个或多个处理器在共享存储器区域中可访问的邮箱区域的接口单元，以提供用于两个或多个处理器之间的通信的接口功能。

公开(公告)号：US20110007576A1

公开(公告)日：2011-01-13

申请号：US12702809

申请日：2010-02-09

Applicant: Sang-kyu Kang ,  Ho-cheol Lee ,  Chi-sung Oh

Inventor： Sang-kyu Kang ,  Ho-cheol Lee ,  Chi-sung Oh

IPC: G11C7/10 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C7/1072 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided is a synchronous dynamic random access memory (DRAM) semiconductor device including multiple output buffers, a strobe control unit and multiple strobe buffers. Each of the output buffers is configured to output one bit of data. The strobe control unit is configured to output multiple strobe control signals in response to an externally input signal. The strobe buffers are connected to the output buffers and the strobe control unit, and each of the strobe buffers is configured to output at least one strobe signal. At least some of the strobe buffers are activated in response to the strobe control signals, and the output buffers are activated in response to the strobe signals output by the activated strobe buffers.

Abstract translation: 提供了包括多个输出缓冲器，选通控制单元和多个选通缓冲器的同步动态随机存取存储器（DRAM）半导体器件。 每个输出缓冲器都配置为输出一位数据。 选通控制单元被配置为响应于外部输入信号输出多个选通控制信号。 选通缓冲器连接到输出缓冲器和选通控制单元，并且每个选通缓冲器被配置为输出至少一个选通信号。 至少一些选通缓冲器响应于选通控制信号被激活，并且输出缓冲器响应于被激活的选通缓冲器输出的选通信号被激活。

公开(公告)号：US20100322021A1

公开(公告)日：2010-12-23

申请号：US12788029

申请日：2010-05-26

Applicant: Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

Inventor： Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

IPC: G11C7/00 ,  G11C8/18

CPC classification number: G11C7/22 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/222 ,  G11C2207/2272

Abstract: A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal.

Abstract translation: 公开了一种半导体存储器件。 半导体器件包括存储单元阵列，时钟信号发生器，被配置为从存储器件的外部接收外部时钟信号并输出​​内部时钟信号;以及数据输出单元，被配置为从存储器单元接收内部数据信号 阵列并响应于内部时钟信号输出读取数据信号。 半导体存储器件还包括读取数据选通单元，其被配置为基于内部时钟信号的周期时间，输出具有n倍（n是等于或大于2的整数）的周期时间的读取数据选通信号 内部时钟信号。

公开(公告)号：US20090254698A1

公开(公告)日：2009-10-08

申请号：US12392432

申请日：2009-02-25

Applicant: Jin-Hyoung KWON ,  Kyung-Woo NAM ,  Han-Gu SOHN ,  Ho-Cheol LEE ,  Kwang-Myeong JANG

Inventor： Jin-Hyoung KWON ,  Kyung-Woo NAM ,  Han-Gu SOHN ,  Ho-Cheol LEE ,  Kwang-Myeong JANG

IPC: G06F12/00

CPC classification number: G11C11/413 ,  G11C7/1075

Abstract: A multiport semiconductor memory device includes; first and second port units respectively coupled to first and second processors, first and second dedicated memory area accessed by first and second processors, respectively and implemented using DRAM cells, a shared memory area commonly accessed by the first and second processors via respective first and second port units and implemented using memory cells different from the DRAM cells implementing the first and second dedicated memory areas, and a port connection control unit controlling data path configuration between the shared memory area and the first and second port units to enable data communication between the first and second processors through the shared memory area.

Abstract translation: 多端口半导体存储器件包括： 分别耦合到第一和第二处理器的第一和第二端口单元，分别由第一和第二处理器访问的第一和第二专用存储器区域，并且使用DRAM单元实现;第一和第二处理器通过相应的第一和第二处理器共同访问的共享存储器区域 端口单元，并且使用与实现第一和第二专用存储区域的DRAM单元不同的存储器单元来实现，以及端口连接控制单元，其控制共享存储区域与第一和第二端口单元之间的数据路径配置，以使得第一 和第二个处理器通过共享内存区域。

公开(公告)号：US07355912B2

公开(公告)日：2008-04-08

申请号：US10268732

申请日：2002-10-11

Applicant: Sang-Kyun Park ,  Ho-Cheol Lee

Inventor： Sang-Kyun Park ,  Ho-Cheol Lee

IPC: G11C7/00

CPC classification number: G11C11/4076 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4094 ,  G11C2207/229

Abstract: An auto-precharge control circuit in a semiconductor memory and method thereof, where the auto-precharge starting point may vary. The auto-precharge starting point may vary in response to at least one control signal. The auto-precharge starting point may vary in accordance with frequency and/or latency information. The auto-precharge starting point may vary in response to at least one control signal including clock frequency information. The auto-precharge starting point may vary depending on a latency signal received from a mode register setting command.

Abstract translation: 半导体存储器中的自动预充电控制电路及其方法，其中自动预充电起点可以变化。 自动预充电起始点可以响应于至少一个控制信号而变化。 自动预充电起始点可以根据频率和/或延迟信息而变化。 响应于包括时钟频率信息的至少一个控制信号，自动预充电起始点可以变化。 自动预充电起点可以根据从模式寄存器设置命令接收到的等待时间信号而变化。

公开(公告)号：US07116627B2

公开(公告)日：2006-10-03

申请号：US09899501

申请日：2001-07-06

Applicant: Jang-hoon Yoo ,  Seung-tae Jung ,  Ho-cheol Lee ,  Ju-hyung Lee ,  Chul-woo Lee ,  Young-il Kim ,  Hyun-seob Choi ,  Sang-beom Hong

Inventor： Jang-hoon Yoo ,  Seung-tae Jung ,  Ho-cheol Lee ,  Ju-hyung Lee ,  Chul-woo Lee ,  Young-il Kim ,  Hyun-seob Choi ,  Sang-beom Hong

IPC: G11B7/00

CPC classification number: G11B7/1374 ,  G11B7/1367 ,  G11B7/13922 ,  G11B2007/0006

Abstract: A compatible optical pickup device includes a single light source to emit a light having a wavelength longer than 650 nm, an objective lens having a near axis area, a ring type annular lens area, and a far axis area to focus the light to form light spots suitable for a first relatively thin optical disk and a second relatively thick optical disk to form a first light spot having an FWHM (full width at half maximum) of 0.72 μm or less for the first optical disk and a second light spot having an FWHM of 0.8 μm or more for the second optical disk, an optical path changer to change a proceeding path of incident light, and a photodetector to receive light reflected by the optical disk and having passed through the objective lens and the optical path changer and to detect an information signal and/or an error signal.

Abstract translation: 兼容的光学拾取装置包括发射波长长于650nm的光的单个光源，具有近轴区域的物镜，环形环形透镜区域和远轴区域，以聚焦光以形成光 适用于第一相对较薄的光盘和第二相对厚的光盘的光点，以形成第一光盘具有FWHM（半高全宽）为0.72μm或更小的第一光点，以及具有FWHM的第二光点 对于第二光盘为0.8μm以上的光路改变器，改变入射光的行进路径的光路改变器，以及光接收器，用于接收由光盘反射并经过物镜和光路变换器的光，并检测 信息信号和/或误差信号。

公开(公告)号：US07079455B2

公开(公告)日：2006-07-18

申请号：US09776706

申请日：2001-02-06

Applicant: Young-min Cheong ,  Cheol-sung Yeon ,  Ho-cheol Lee ,  Dong-seob Jang ,  Gyu-chan Jun

Inventor： Young-min Cheong ,  Cheol-sung Yeon ,  Ho-cheol Lee ,  Dong-seob Jang ,  Gyu-chan Jun

IPC: G11B7/00

CPC classification number: G11B7/1384 ,  G11B7/08576 ,  G11B7/0929 ,  G11B7/0932 ,  G11B7/0933 ,  G11B7/0935 ,  G11B7/122 ,  G11B7/1356

Abstract: An optical reading and writing system including a base; an optical disk rotatably mounted on the base; an optical pickup including an objective lens, focusing a light beam to form a light spot on a recording surface of the optical disk; an actuator arm mounted on the base such that the actuator arm can pivot in the radial direction of the optical disk by a voice coil motor; a load beam supported by the actuator arm, and capable of moving slightly up and down and in the radial direction of the optical disk by an external force; a flexure attached to the load beam, supporting a slider to enable the slider to contact the recording surface; and a driving unit mounted on free ends of the actuator arm and the load beam, providing a driving force in the radial direction to the free end of the load beam.

Abstract translation: 一种包括基座的光学读写系统; 可旋转地安装在基座上的光盘; 包括物镜的光学拾取器，聚焦光束以在光盘的记录表面上形成光斑; 安装在基座上的致动器臂，使得致动器臂可以通过音圈电机在光盘的径向方向上枢转; 由致动器臂支撑并且能够通过外力稍微上下移动并且在光盘的径向方向上移动的负载梁; 附接到负载梁的挠曲件，支撑滑块以使滑块能够接触记录表面; 以及驱动单元，其安装在致动器臂和负载梁的自由端上，在径向方向上向负载梁的自由端提供驱动力。