公开(公告)号：US08625381B2

公开(公告)日：2014-01-07

申请号：US13026460

申请日：2011-02-14

Applicant: Ho-Cheol Lee

Inventor： Ho-Cheol Lee

IPC: G11C5/06 ,  G11C5/02 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  G11C8/02 ,  G11C8/12 ,  G11C8/10

CPC classification number: H01L23/544 ,  H01L24/04 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552

Abstract: Provided is a stacked semiconductor device including n stacked chips. Each chip includes “j” corresponding upper and lower electrodes, wherein j is a minimal natural number greater than or equal to n/2, and an identification code generator including a single inverter connecting one of the j first upper electrode to a corresponding one of the j lower electrodes. The upper electrodes receive a previous identification code, rotate the previous identification code by a unit of 1 bit, and invert 1 bit of the rotated previous identification code to generate a current identification code. The current identification code is applied through the j lower electrodes and corresponding TSVs to communicate the current identification code to the upper adjacent chip.

Abstract translation: 提供了包括n个堆叠芯片的堆叠半导体器件。 每个芯片包括对应的上部和下部电极的“j”，其中j是大于或等于n / 2的最小自然数，以及识别码发生器，其包括将j个第一上电极中的一个连接到 j个下电极。 上电极接收先前的识别码，以1位为单位旋转先前的识别码，并且反转已转动的先前识别码的1位，以产生当前识别码。 通过j个下部电极和相应的TSV施加当前的识别码，以将当前识别码传送到上部相邻的芯片。

公开(公告)号：US20110093235A1

公开(公告)日：2011-04-21

申请号：US12900547

申请日：2010-10-08

Applicant: CHI-SUNG OH ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

Inventor： CHI-SUNG OH ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

IPC: G01R31/14 ,  H03L7/00

CPC classification number: G01R31/2884 ,  G01R31/31726

Abstract: A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.

Abstract translation: 提供半导体器件。 半导体器件将通过测试焊盘安装有凸块的凸块焊盘施加的数据施加到测试装置，使得可以提高测试的可靠性。 通过允许通过凸块焊盘的数据输出被选择性地施加到测试焊盘，测试焊盘的量显着减少。 从测试焊盘施加的数据和信号彼此同步，并在测试操作期间应用于凸块焊盘，从而可以提高测试的可靠性，而无需额外的测试芯片。

公开(公告)号：US07870326B2

公开(公告)日：2011-01-11

申请号：US11819601

申请日：2007-06-28

Applicant: Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

Inventor： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

IPC: G06F12/00

CPC classification number: G06F12/02

Abstract: A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

Abstract translation: 提供了一种多处理器系统及其方法。 示例性多处理器系统可以包括第一和第二处理器，具有存储单元阵列的动态随机存取存储器，所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组，耦合到第二存储器组的第二存储器组和第四存储器组 处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组，以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元，如同样的 通过第一和第二端口的存储器地址，使得第一和第二存储器组的起始地址在引导中变得相等，并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址， 通过第二个端口，银行地址选择第四个存储器，作为与银行地址相同的银行地址，选择第三个存储器 银行通过第一个港口。

公开(公告)号：US20080205175A1

公开(公告)日：2008-08-28

申请号：US12068280

申请日：2008-02-05

Applicant: Sang-Kyun Park ,  Ho-Cheol Lee

Inventor： Sang-Kyun Park ,  Ho-Cheol Lee

IPC: G11C7/00

CPC classification number: G11C11/4076 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4094 ,  G11C2207/229

Abstract: An auto-precharge control circuit in a semiconductor memory and method thereof, where the auto-precharge starting point may vary. The auto-precharge starting point may vary in response to at least one control signal. The auto-precharge starting point may vary in accordance with frequency and/or latency information. The auto-precharge starting point may vary in response to at least one control signal including clock frequency information. The auto-precharge starting point may vary depending on a latency signal received from a mode register setting command. The auto-precharge control circuit may include a control circuit for receiving a write signal, a clock signal and at least one control signal, including at least one of clock frequency information and latency information, and outputting at least one path signal; an auto-precharge pulse signal driver for receiving the at least one path signal, the write signal, and an enable signal and producing an auto-precharge pulse signal, the auto-precharge pulse signal identifying a starting point for an auto-precharge operation; and an auto-precharge mode enabling circuit for receiving the clock signal, an auto-precharge command, an active signal, and the auto-precharge pulse signal and generating the enable signal.

Abstract translation: 半导体存储器中的自动预充电控制电路及其方法，其中自动预充电起点可以变化。 自动预充电起始点可以响应于至少一个控制信号而变化。 自动预充电起始点可以根据频率和/或延迟信息而变化。 响应于包括时钟频率信息的至少一个控制信号，自动预充电起始点可以变化。 自动预充电起点可以根据从模式寄存器设置命令接收到的等待时间信号而变化。 自动预充电控制电路可以包括用于接收包括时钟频率信息和等待时间信息中的至少一个的写入信号，时钟信号和至少一个控制信号的控制电路，并且输出至少一个路径信号; 自动预充电脉冲信号驱动器，用于接收至少一个路径信号，写入信号和使能信号，并产生自动预充电脉冲信号，所述自动预充电脉冲信号标识自动预充电操作的起始点; 以及自动预充电模式使能电路，用于接收时钟信号，自动预充电命令，有效信号和自动预充电脉冲信号，并产生使能信号。

公开(公告)号：US06928023B2

公开(公告)日：2005-08-09

申请号：US10465553

申请日：2003-06-20

Applicant: Ho-Cheol Lee ,  Jung-Soo Ryoo

Inventor： Ho-Cheol Lee ,  Jung-Soo Ryoo

IPC: G11C7/00 ,  G11C5/06 ,  G11C5/14 ,  G11C8/12

CPC classification number: G11C5/063 ,  G11C5/14 ,  G11C8/12

Abstract: A method of controlling a bank voltage (AIVC) through memory block selection information, said method comprising the steps of detecting an array block selection signal of an array block disposed distantly from an AIVC driver in response to an activated memory array block selection signal; and supplying a second bank voltage to a memory bank by driving a normal size driver and an oversize driver when detecting the array block selection signal for the distantly disposed array block.

Abstract translation: 一种通过存储块选择信息控制存储体电压（AIVC）的方法，所述方法包括以下步骤：响应激活的存储器阵列块选择信号，检测远离AIVC驱动器的阵列块的阵列块选择信号; 以及当检测到用于远处布置的阵列块的阵列块选择信号时，通过驱动正常尺寸的驱动器和超大驱动器，将第二存储体电压提供给存储体。

公开(公告)号：US5631871A

公开(公告)日：1997-05-20

申请号：US578151

申请日：1995-12-29

Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  B01F7/00 ,  B01F13/00

CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

公开(公告)号：US5598371A

公开(公告)日：1997-01-28

申请号：US565292

申请日：1995-11-30

Applicant: Ho-Cheol Lee ,  Seung-Hun Lee

Inventor： Ho-Cheol Lee ,  Seung-Hun Lee

IPC: G11C11/417 ,  G11C7/10 ,  G11C11/409 ,  G11C13/00 ,  G11C7/00

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/1078

Abstract: A data input/output sensing circuit of a semiconductor memory device including a plurality of memory cells, the circuit comprises: input/output lines of the memory cell; data input/output terminals connected to outside of the memory cells; a single data input/output line connected between the input/output lines and the data input/output terminals; a sensing unit for sensing whether or not effective data is provided in the data input/output lines to thereby generate a sensing signal; an output driving unit for transmitting data of the data input/output lines to the data input/output terminals in response to the sensing signal; and a writing driving unit for inputting data of the data input/output terminals in response to the sensing signal.

Abstract translation: 一种包括多个存储单元的半导体存储器件的数据输入/输出感测电路，该电路包括：存储单元的输入/输出线; 连接到存储单元外部的数据输入/输出端子; 连接在输入/输出线路和数据输入/输出端子之间的单个数据输入/输出线路; 感测单元，用于检测数据输入/输出线中是否提供有效数据，从而产生感测信号; 输出驱动单元，用于响应于感测信号将数据输入/输出线的数据发送到数据输入/输出端; 以及写入驱动单元，用于响应于感测信号输入数据输入/输出端子的数据。

公开(公告)号：US5191484A

公开(公告)日：1993-03-02

申请号：US828120

申请日：1992-01-30

Applicant: Jye-Sye Yeon ,  Jong-Jin Lee ,  Ho-Cheol Lee

Inventor： Jye-Sye Yeon ,  Jong-Jin Lee ,  Ho-Cheol Lee

IPC: G11B7/09

CPC classification number: G11B7/0935

Abstract: An optical pick-up objective lens driving apparatus comprises a rectangular moving member mounted for movement relative to an iron-core member in rectilinear focusing and tracking directions, respectively. The moving member carries focusing and tracking coils, and a lens. Magnetic pieces are disposed at respective corners of the moving member in opposing spacial relationship to magnetic plates of the iron core member to create a restoring force which biases the moving member to a pre-set position. The lens is mounted over a center of weight of the moving member.

Abstract translation: 光学拾取物镜驱动装置包括分别安装成相对于铁芯件在直线聚焦和跟踪方向上移动的矩形移动部件。 移动构件携带聚焦跟踪线圈和透镜。 磁片以与铁芯构件的磁性板相对的空间关系设置在移动构件的各个角上，以产生将移动构件偏压到预定位置的恢复力。 透镜安装在移动部件的重心上。

公开(公告)号：US08122199B2

公开(公告)日：2012-02-21

申请号：US12392432

申请日：2009-02-25

Applicant: Jin-Hyoung Kwon ,  Kyung-Woo Nam ,  Han-Gu Sohn ,  Ho-Cheol Lee ,  Kwang-Myeong Jang

Inventor： Jin-Hyoung Kwon ,  Kyung-Woo Nam ,  Han-Gu Sohn ,  Ho-Cheol Lee ,  Kwang-Myeong Jang

IPC: G06F12/00

CPC classification number: G11C11/413 ,  G11C7/1075

Abstract: A multiport semiconductor memory device includes; first and second port units respectively coupled to first and second processors, first and second dedicated memory area accessed by first and second processors, respectively and implemented using DRAM cells, a shared memory area commonly accessed by the first and second processors via respective first and second port units and implemented using memory cells different from the DRAM cells implementing the first and second dedicated memory areas, and a port connection control unit controlling data path configuration between the shared memory area and the first and second port units to enable data communication between the first and second processors through the shared memory area.

Abstract translation: 多端口半导体存储器件包括： 分别耦合到第一和第二处理器的第一和第二端口单元，分别由第一和第二处理器访问的第一和第二专用存储器区域，并且使用DRAM单元实现;第一和第二处理器通过相应的第一和第二处理器共同访问的共享存储器区域 端口单元，并且使用与实现第一和第二专用存储区域的DRAM单元不同的存储器单元来实现，以及端口连接控制单元，其控制共享存储区域与第一和第二端口单元之间的数据路径配置，以使得第一 和第二个处理器通过共享内存区域。

公开(公告)号：US20120038045A1

公开(公告)日：2012-02-16

申请号：US13110433

申请日：2011-05-18

Applicant: Ho-Cheol Lee

Inventor： Ho-Cheol Lee

IPC: H01L23/498 ,  H01L23/48 ,  H01L21/50

CPC classification number: H01L24/97 ,  H01L23/3107 ,  H01L23/481 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00

Abstract: A stacked semiconductor device may have a plurality of chips stacked in three-dimension. The stacked semiconductor device may include a first semiconductor chip and at least one second semiconductor chip. The first semiconductor chip may include a plurality of first through silicon vias (TSVs). The at least one second semiconductor chip may include a plurality of second TSVs. The at least one second semiconductor chip may be stacked above the first semiconductor chip and may be thinner than the first semiconductor chip. Therefore, the stacked semiconductor device may have an improved reliability.

Abstract translation: 叠层半导体器件可以具有三维堆叠的多个芯片。 层叠的半导体器件可以包括第一半导体芯片和至少一个第二半导体芯片。 第一半导体芯片可以包括多个第一至第二通孔（TSV）。 所述至少一个第二半导体芯片可以包括多个第二TSV。 所述至少一个第二半导体芯片可以堆叠在第一半导体芯片之上并且可以比第一半导体芯片更薄。 因此，堆叠式半导体器件可以具有改善的可靠性。