System and method for interleaving memory banks
    62.
    发明授权
    System and method for interleaving memory banks 失效
    用于交织存储器的系统和方法

    公开(公告)号:US5579277A

    公开(公告)日:1996-11-26

    申请号:US432908

    申请日:1995-05-01

    申请人: James D. Kelly

    发明人: James D. Kelly

    IPC分类号: G11C8/12 G11C13/00

    CPC分类号: G11C8/12

    摘要: A device and method are provided for mapping address bus bits to memory address by using interleaved and non-interleaved modes so that every desired row and column configuration stored in a register file may be supported. Also, the device and method allow a combination of interleaved and non-interleaved memory bank pairs to be used by registering row and column address in a plurality of registers corresponding to interleaved and non-interleaved combinations. In particular, the memory bank pairs which are capable of being interleaved have the interleaved operation performed automatically while the memory bank pairs which cannot be interleaved have the non-interleaved operation performed thereon. As a result, the performance of the memory is enhanced while eliminating the amount of user interface necessary.

    摘要翻译: 提供了一种设备和方法,用于通过使用交错和非交织模式将地址总线位映射到存储器地址,从而可以支持存储在寄存器文件中的每个期望的行和列配置。 此外,该装置和方法允许通过在对应于交错和非交织的组合的多个寄存器中注册行和列地址来使用交织和非交织的存储体对的组合。 特别地,能够被交织的存储体对具有自动执行的交织操作,而不能被交织的存储体对具有在其上执行的非交织操作。 结果,提高了存储器的性能,同时消除了需要的用户界面的数量。

    Method and system for improving bus utilization efficiency
    63.
    发明授权
    Method and system for improving bus utilization efficiency 失效
    提高总线利用效率的方法和系统

    公开(公告)号:US5557755A

    公开(公告)日:1996-09-17

    申请号:US201461

    申请日:1994-02-24

    IPC分类号: G06F13/40 G06F13/36 G06F13/42

    CPC分类号: G06F13/4022

    摘要: In a bus system including a bus, a plurality of nodes including a primary node, and a bus access coordinator, bus utilization efficiency is improved by operating the coordinator at the same clock frequency as the primary node. The primary node is the node in the bus system which accesses the bus most frequently. By running the coordinator synchronous with the primary node, the need for synchronization events between the two components is eliminated. Since the primary node accesses the bus most frequently, eliminating synchronization events with the primary node eliminates most of the synchronization events in the bus system. Thus, synchronization events are minimized which, in turn, improves bus utilization efficiency.

    摘要翻译: 在包括总线,包括主节点的多个节点和总线访问协调器的总线系统中,通过以与主节点相同的时钟频率操作协调器来提高总线利用效率。 主节点是总线系统中最频繁访问总线的节点。 通过运行与主节点同步的协调器,消除了两个组件之间的同步事件的需要。 由于主节点最频繁地访问总线,消除与主节点的同步事件消除了总线系统中的大部分同步事件。 因此,同步事件被最小化,这又提高总线利用效率。