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    CONTEXT AWARE SUB-CIRCUIT LAYOUT MODIFICATION
    62.
    发明申请
    CONTEXT AWARE SUB-CIRCUIT LAYOUT MODIFICATION 失效
    背景知识子电路布局修改

    公开(公告)号：US20090037851A1

    公开(公告)日：2009-02-05

    申请号：US11831998

    申请日：2007-08-01

    Applicant: Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Robert F. Walker ,  Xin Yuan

    Inventor： Michael S. Gray ,  Matthew T. Guzowski ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Robert F. Walker ,  Xin Yuan

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: A method, system and program product for context aware sub-circuit layout modification are disclosed. The method may include defining at least one context for the sub-circuit for each circuit that uses the sub-circuit; in the case that a plurality of contexts are defined, minimizing a number of contexts for the sub-circuit by combining contexts into at least one stage; placing each stage into a staged layout; and modifying the sub-circuit by modifying the staged layout.

    Abstract translation: 公开了一种用于上下文感知子电路布局修改的方法，系统和程序产品。 该方法可以包括为使用子电路的每个电路定义用于子电路的至少一个上下文; 在定义多个上下文的情况下，通过将上下文合并到至少一个级中来最小化子电路的上下文数量; 将每个阶段放置在分阶段布局中; 并通过修改分段布局修改子电路。

    METHOD OF OPTIMIZING HIERARCHICAL VERY LARGE SCALE INTEGRATION (VLSI) DESIGN BY USE OF CLUSTER-BASED LOGIC CELL CLONING
    64.
    发明申请
    METHOD OF OPTIMIZING HIERARCHICAL VERY LARGE SCALE INTEGRATION (VLSI) DESIGN BY USE OF CLUSTER-BASED LOGIC CELL CLONING 审中-公开
    通过使用基于群集的逻辑单元克隆优化分层级非常大规模集成（VLSI）设计的方法

    公开(公告)号：US20080172638A1

    公开(公告)日：2008-07-17

    申请号：US11623122

    申请日：2007-01-15

    Applicant: Michael S. Gray ,  David J. Hathaway ,  Jason D. Hibbeler ,  Robert F. Walker ,  Xin Yuan

    Inventor： Michael S. Gray ,  David J. Hathaway ,  Jason D. Hibbeler ,  Robert F. Walker ,  Xin Yuan

    IPC: G06F17/50

    CPC classification number: G06F17/5045

    Abstract: A method of optimizing hierarchical very large scale integration (VLSI) design by use of cluster-based cell cloning. The method of the present invention provides improved yield or migration by reusing cells in order to reduce the number of unique instances of at least one of the reused cells. The method performs hierarchal optimization on the reduced set of clones (i.e., clusters). The method of the present disclosure includes, but is not limited to, the steps of setting the initial clustering parameters; assembling the physical design from existing reused cells; for each cell type, performing a full cloning operation in order to create a full set of duplicate cells; for each cell type, performing a full optimization of the design; for each cell type, performing an analyses of all cell environments and performing a clustering operation; and analyzing the overall results in order to determine whether the optimization objectives are achieved.

    Abstract translation: 通过使用基于簇的细胞克隆来优化分级超大规模集成（VLSI）设计的方法。 本发明的方法通过重新使用细胞来提供改善的产量或迁移，以减少至少一个重复使用的细胞的唯一实例的数量。 该方法对减少的克隆集合（即，簇）执行层次优化。 本公开的方法包括但不限于设置初始聚类参数的步骤; 从现有的重复使用的电池组装物理设计; 对于每个单元格类型，执行完全克隆操作以便创建一整套重复的单元格; 对于每个单元格类型，执行设计的全面优化; 对于每个单元类型，执行所有单元环境的分析并执行聚类操作; 并分析总体结果，以确定是否实现优化目标。

    Yield optimization in router for systematic defects
    65.
    发明授权
    Yield optimization in router for systematic defects 失效
    路由器产生优化系统缺陷

    公开(公告)号：US07398485B2

    公开(公告)日：2008-07-08

    申请号：US11279262

    申请日：2006-04-11

    Applicant: Jeanne P. Bickford ,  Markus T. Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Daniel N. Maynard

    Inventor： Jeanne P. Bickford ,  Markus T. Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Daniel N. Maynard

    IPC: G06F17/50

    CPC classification number: G06F17/5077

    Abstract: Embodiments herein provide a method and computer program product for optimizing router settings to increase IC yield. A method begins by reviewing yield data in an IC manufacturing line to identify structure-specific mechanisms that impact IC yield. Next, the method establishes a structural identifier for each structure-specific mechanism, wherein the structural identifiers include wire codes, tags, and/or unique identifiers. Different structural identifiers are established for wires having different widths. Furthermore, the method establishes a weighting factor for each structure-specific mechanism, wherein higher weighting factors are established for structure-specific mechanisms comprising thick wires proximate to multiple thick wires. The method establishes the structural identifiers and the weighting factors for incidence of spacing between single wide lines, double wide lines, and triple wide lines and for incidence of wires above large metal lands. Subsequently, the router settings are modified based on the structural identifiers and the weighting factors to minimize systematic defects.

    Abstract translation: 本文的实施例提供了一种用于优化路由器设置以增加IC产量的方法和计算机程序产品。 一种方法开始于检查IC生产线中的产量数据，以确定影响IC产量的结构特异性机制。 接下来，该方法为每个结构特定机制建立结构标识符，其中结构标识符包括有线代码，标签和/或唯一标识符。 针对具有不同宽度的电线建立了不同的结构标识符。 此外，该方法为每个结构特定机构建立加权因子，其中针对包括靠近多个粗线的粗线的结构特定机构建立较高的加权因子。 该方法建立了单宽线，双宽线和三宽线之间的间距发生的结构标识符和加权因子，以及大金属土地上电线的入射。 随后，路由器设置基于结构标识符和权重因子进行修改，以最大限度地减少系统缺陷。

    Test yield estimate for semiconductor products created from a library
    66.
    发明授权
    Test yield estimate for semiconductor products created from a library 有权
    从图书馆创建的半导体产品的测试产量估算

    公开(公告)号：US07386815B2

    公开(公告)日：2008-06-10

    申请号：US11163696

    申请日：2005-10-27

    Applicant: Jeanne Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl

    Inventor： Jeanne Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    Abstract: Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For example, the method considers the test yield impact of sensitivity to library element to library element shorts and the test yield impact of sensitivity to wiring faults. The disclosed method further allows die size growth to be traded off against the use of library elements with higher test yield in order to provide an optimal design solution. Thus, the method may be used to modify library element selection so as to optimize test yield. Lastly, the method further repeats itself at key design checkpoints to revalidate initial test yield (and cost) assumptions made when the product was quoted to a customer. Thus, the method provides increased accuracy of test yield estimate from initial sizing through design and further allows designs to be modified to improve test yield.

    Abstract translation: 公开了一种在设计布局之前预测半导体产品的测试产量的方法。 这是通过对用于形成特定产品的单个库元素应用关键区域分析，并通过估计组合这些库元素的测试产出影响来实现的。 例如，该方法考虑了库元素对库元素短路的灵敏度的测试产量影响以及对接线故障的灵敏度的测试产量影响。 所公开的方法进一步允许模具尺寸增长与使用具有较高测试成品率的库元件进行交易，以便提供最佳设计解决方案。 因此，该方法可用于修改库元素选择以优化测试产量。 最后，该方法在关键设计检查点进一步重复，以重新验证产品被引用给客户时的初始测试收益（和成本）假设。 因此，该方法通过设计从初始尺寸提高了测试产量估算的准确度，并进一步允许修改设计以提高测试产量。

    Integrated circuit yield enhancement using Voronoi diagrams
    67.
    发明授权
    Integrated circuit yield enhancement using Voronoi diagrams 有权
    使用Voronoi图的集成电路产量增强

    公开(公告)号：US07260790B2

    公开(公告)日：2007-08-21

    申请号：US10709292

    申请日：2004-04-27

    Applicant: Robert J. Allen ,  Michael S. Gray ,  Jason D. Hibbeler ,  Mervyn Yee-Min Tan ,  Robert F. Walker

    Inventor： Robert J. Allen ,  Michael S. Gray ,  Jason D. Hibbeler ,  Mervyn Yee-Min Tan ,  Robert F. Walker

    IPC: G06F17/50

    CPC classification number: G06F17/5081

    Abstract: A method of calculating critical area in an integrated circuit design, said method comprising: inputting an integrated circuit design; associating variables with the positions of edges in said integrated circuit design; and associating cost functions of said variables with spacing between said edges in said integrated circuit design; wherein said cost functions calculate critical area contributions as the positions and length of said edges in said integrated circuit design change, and wherein said critical area contributions comprise a measure of electrical fault characteristics of said spacing between said edges in said integrated circuit design.

    Abstract translation: 一种在集成电路设计中计算临界面积的方法，所述方法包括：输入集成电路设计; 将变量与所述集成电路设计中的边缘的位置相关联; 以及将所述变量的成本函数与所述集成电路设计中的所述边缘之间的间隔相关联; 其中当所述集成电路设计中的所述边缘的位置和长度改变时，所述成本函数计算临界面积贡献，并且其中所述临界区域贡献包括所述集成电路设计中所述边缘之间的所述间隔的电气故障特征的量度。

    Automated configuration of on-circuit facilities
    68.
    发明授权
    Automated configuration of on-circuit facilities 失效
    自动配置电路设备

    公开(公告)号：US06970809B2

    公开(公告)日：2005-11-29

    申请号：US09941306

    申请日：2001-08-29

    Applicant: Cheng A. Feng ,  Jason D. Hibbeler ,  Theodore G. Hoover, Jr. ,  Judith K. Ingles ,  Jhy-Chun Wang

    Inventor： Cheng A. Feng ,  Jason D. Hibbeler ,  Theodore G. Hoover, Jr. ,  Judith K. Ingles ,  Jhy-Chun Wang

    IPC: G06F11/34 ,  G06F19/00

    CPC classification number: G06F11/348

    Abstract: A system and method for configuring a plurality of monitors, which are contained within a complex circuit, to monitor a valid combination of events within the complex circuit. Each monitor of the complex circuit is only able to monitor a subset of the total set of events which may be monitored. The present invention allows a user to select valid associations between events and monitors, and then processes those selected associations for configuration of the complex circuit. The selected associations may be stored and reused in the future.

    Abstract translation: 一种用于配置包含在复杂电路内的多个监视器的系统和方法，用于监视复合电路内事件的有效组合。 复杂电路的每个监视器只能监视可能被监视的整组事件的子集。 本发明允许用户选择事件和监视器之间的有效关联，然后处理这些所选择的关联以配置复杂电路。 所选择的关联可以在将来被存储和重复使用。

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