公开(公告)号：US20130158342A1

公开(公告)日：2013-06-20

申请号：US13543137

申请日：2012-07-06

Applicant: Barbara Chan ,  Timothy Shane Johnson ,  Irene E. Kochevar ,  Mark Randolph ,  Robert W. Redmond ,  Jonathan M. Winograd

Inventor： Barbara Chan ,  Timothy Shane Johnson ,  Irene E. Kochevar ,  Mark Randolph ,  Robert W. Redmond ,  Jonathan M. Winograd

IPC: A61B17/11

CPC classification number: A61B17/11 ,  A61B2017/00508 ,  A61B2017/00517 ,  A61F9/0079 ,  A61F9/0081 ,  A61F9/00821 ,  A61F2009/00842 ,  A61F2009/00853 ,  A61F2009/00872 ,  A61F2009/00887 ,  A61L24/001 ,  A61L2430/32 ,  A61N5/062

Abstract: Photochemical tissue boding methods for bonding neural tissues include the application of a photosensitizer to a tissue and/or tissue graft, followed by irradiation with electromagnetic energy to produce a tissue seal. The methods are useful for tissue adhesion, such as in wound closure, tissue grafting, skin grafting, musculoskeletal tissue repair, ligament or tendon repair, neural repair, blood vessel repair and corneal repair.

Abstract translation: 用于粘合神经组织的光化学组织编织方法包括将光敏剂施用于组织和/或组织移植物，随后用电磁能照射以产生组织密封。 该方法可用于组织粘连，例如伤口闭合，组织移植，皮肤移植，肌肉骨骼组织修复，韧带或肌腱修复，神经修复，血管修复和角膜修复。

公开(公告)号：US07492001B2

公开(公告)日：2009-02-17

申请号：US11086310

申请日：2005-03-23

Applicant: Wei Zheng ,  Mark Randolph ,  Hidehiko Shiraiwa

Inventor： Wei Zheng ,  Mark Randolph ,  Hidehiko Shiraiwa

IPC: H01L29/788 ,  H01L29/72

CPC classification number: H01L29/792 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282

Abstract: A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.

Abstract translation: 存储器件可以包括形成在衬底中的源极区域和漏极区域以及形成在源极和漏极区域之间的衬底中的沟道区域。 存储器件还可以包括形成在沟道区上的第一氧化物层，第一氧化物层具有第一介电常数，以及形成在第一氧化物层上的电荷存储层。 存储器件还可以包括形成在电荷存储层上的第二氧化物层，形成在第二氧化物层上的介电材料层，介电材料具有大于第一介电常数的第二介电常数，以及栅电极 形成在电介质材料层上。

公开(公告)号：US07402868B2

公开(公告)日：2008-07-22

申请号：US10976816

申请日：2004-11-01

Applicant: Ihsan Jahed Djomehri ,  Mark Randolph ,  Yi He ,  Wei Zheng

Inventor： Ihsan Jahed Djomehri ,  Mark Randolph ,  Yi He ,  Wei Zheng

IPC: H01L23/62

CPC classification number: H01L27/115 ,  H01L27/0288

Abstract: A semiconductor memory device includes a group of word lines and a structure that is configured to dissipate current from the group of word lines during fabrication of the semiconductor memory device.

Abstract translation: 半导体存储器件包括一组字线和被配置成在制造半导体存储器件期间消散来自字线组的电流的结构。

公开(公告)号：US20080142889A1

公开(公告)日：2008-06-19

申请号：US11612265

申请日：2006-12-18

Applicant: Wei ZHENG ,  Jean YANG ,  Mark RANDOLPH ,  Ming KWAN ,  Yi HE ,  Zhizheng LIU ,  Meng DING

Inventor： Wei ZHENG ,  Jean YANG ,  Mark RANDOLPH ,  Ming KWAN ,  Yi HE ,  Zhizheng LIU ,  Meng DING

IPC: H01L23/62 ,  H01L29/76 ,  H01L21/336

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11531

Abstract: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Abstract translation: 半导体器件包括衬底和形成在衬底上的存储单元。 存储单元包括字线。 半导体器件还包括形成在衬底中的保护区域，被配置为将字线延伸到保护区域的导电结构以及被配置为使字线和保护区域短路的触点。

公开(公告)号：US07206224B1

公开(公告)日：2007-04-17

申请号：US11037477

申请日：2005-01-18

Applicant: Mark Randolph ,  Darlene Hamilton ,  Roni Kornitz

Inventor： Mark Randolph ,  Darlene Hamilton ,  Roni Kornitz

IPC: G11C11/34

CPC classification number: G11C16/0475 ,  G11C16/10 ,  G11C2211/5641

Abstract: Methods and circuits for performing high speed write (programming) operations in a dual-bit flash memory array. The method includes, for example, erasing a first and second bit of each cell in the array to a first state, programming the first bit of each cell in the array to a second state, and subsequently programming the second bit of one or more cells in the array to one of the first and second state according to the user's data, resulting in fast write (programming) of those second bits. In addition, the circuit includes, for example, a core cell array having dual-bit flash memory cells configured into a plurality of array portions. The circuit further includes a control circuit configured to selectively block erase one of the array portions, wherein in a first phase of the block erase both first and second bit locations of each dual-bit flash memory cell in the one array portion have sufficient charge removed therefrom to achieve a first state. The control circuit is further configured to, in a second phase of the block erase, supply charge to the first bit location of each dual-bit flash memory cell of the one array portion to enable subsequently fast-write of user's data to the second bit location.

公开(公告)号：US20060291282A1

公开(公告)日：2006-12-28

申请号：US11511763

申请日：2006-08-29

Applicant: Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

Inventor： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

IPC: G11C11/34

CPC classification number: G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/66833

Abstract: Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

公开(公告)号：US20060268593A1

公开(公告)日：2006-11-30

申请号：US11136981

申请日：2005-05-25

Applicant: Meng Ding ,  Zhizheng Liu ,  Yi He ,  Mark Randolph

Inventor： Meng Ding ,  Zhizheng Liu ,  Yi He ,  Mark Randolph

IPC: G11C17/00

CPC classification number: G11C17/16 ,  G11C2213/72 ,  H01L27/1021 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/118

Abstract: According to one exemplary embodiment, a programmable ROM array includes at least one bitline situated in a substrate. The programmable ROM array further includes at least one wordline situated over the at least one bitline. The programmable ROM array further includes a memory cell situated at an intersection of the at least one bitline and the at least one wordline, where the memory cell includes a dielectric region situated between the at least one bitline and the at least one wordline. A programming operation causes the memory cell to change from a first logic state to a second logic state by causing the dielectric region to break down. The programming operation causes the memory cell to operate as a diode. A resistance of the memory cell can be measured in a read operation to determine if the memory cell has the first or second logic state.

Abstract translation: 根据一个示例性实施例，可编程ROM阵列包括位于衬底中的至少一个位线。 可编程ROM阵列还包括位于至少一个位线上的至少一个字线。 可编程ROM阵列还包括位于所述至少一个位线和所述至少一个字线的交叉点处的存储器单元，其中所述存储器单元包括位于所述至少一个位线和所述至少一个字线之间的电介质区域。 通过使介电区域分解，编程操作使存储单元从第一逻辑状态变为第二逻辑状态。 编程操作使存储单元作为二极管工作。 可以在读取操作中测量存储器单元的电阻，以确定存储单元是否具有第一或第二逻辑状态。

公开(公告)号：US07120063B1

公开(公告)日：2006-10-10

申请号：US10841850

申请日：2004-05-07

Applicant: Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

Inventor： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/66833

Abstract: Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

Abstract translation: 提供了闪存单元，其包括形成在衬底沟道区上方的电介质材料，在电介质材料上形成的电荷俘获材料，以及形成在电荷俘获材料上的控制栅。 可以通过将电子从控制栅极引导到电荷捕获材料中来提高电池阈值电压来编程电池。 电子可以通过将衬底耦合到衬底电压电势，并将控制栅极耦合到栅极电压电位，其中栅极电压电位低于衬底电压电位，从控制栅极引导到电荷俘获材料。 可以通过将电子从电荷捕获材料引入控制栅极来降低闪速存储器单元的阈值电压，例如通过将衬底耦合到衬底电压电位，以及将控制栅极耦合到栅极电压电位来擦除电池 ，其中栅极电压电位高于衬底电压电位。

公开(公告)号：US07069633B2

公开(公告)日：2006-07-04

申请号：US10920655

申请日：2004-08-17

Applicant: Rosendo Camacho ,  Mark Randolph Robbins

Inventor： Rosendo Camacho ,  Mark Randolph Robbins

IPC: B23P6/00

CPC classification number: B60J1/1815 ,  B60J7/123 ,  Y10T29/49718 ,  Y10T29/49721 ,  Y10T29/4973

Abstract: A process for replacing a first soft-top of a convertible-top of a motor vehicle with a second soft-top includes separating the first soft-top from a headliner of the convertible-top and removing the first soft-top from the convertible top. The second soft-top is selected. The second soft-top has a window at least as large as a window of the first soft-top. A plurality of receptacles are fixed to the second soft-top. The second soft-top is attached to the motor vehicle. The second soft-top is connected directly to the headliner by engaging headliner anchors with the receptacles fixed to the second soft-top.

Abstract translation: 用第二软顶盖替换机动车辆的敞篷车顶部的第一软顶的过程包括将第一软顶与顶篷的顶篷分开，并从可转换顶部移除第一软顶 。 选择第二个软顶。 第二软顶具有至少与第一软顶的窗口一样大的窗口。 多个插座固定到第二软顶。 第二个软顶连接到汽车上。 第二软顶通过将顶篷锚固件与固定到第二软顶的容器接合而直接连接到顶篷。

公开(公告)号：US07051413B2

公开(公告)日：2006-05-30

申请号：US10803773

申请日：2004-03-17

Applicant: Rosendo Camacho ,  Mark Randolph Robbins

Inventor： Rosendo Camacho ,  Mark Randolph Robbins

IPC: B23P6/00

CPC classification number: B60J1/1815 ,  B60J7/123 ,  Y10T29/49716 ,  Y10T29/49718 ,  Y10T29/4973

Abstract: A process for replacing a first soft-top of a convertible-top of a motor vehicle with a second soft-top includes removing the first soft-top from the convertible-top. The first soft-top is separated from a headliner of the convertible-top. The second soft-top is selected. The second soft-top has a window larger than a window of the first soft-top. A plurality of receptacles are fixed to an edge of the larger window. The second soft-top is attached to the motor vehicle. The larger window is connected directly to the headliner by engaging headliner anchors with the receptacles fixed to the larger window.

Abstract translation: 用第二软顶座替换机动车辆的敞篷车顶部的第一软顶的过程包括从敞篷车顶部移除第一软顶。 第一个软顶与敞篷车顶棚分开。 选择第二个软顶。 第二软顶具有大于第一软顶的窗口的窗口。 多个插座固定在较大窗口的边缘上。 第二个软顶连接到汽车上。 较大的窗口通过将顶篷锚固件与固定到较大窗口的容器接合而直接连接到顶篷。