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    ERROR-DIFFUSION BASED TEMPORAL DITHERING FOR COLOR DISPLAY DEVICES
    64.
    发明申请
    ERROR-DIFFUSION BASED TEMPORAL DITHERING FOR COLOR DISPLAY DEVICES 审中-公开
    用于彩色显示设备的基于误差扩展的时间抖动

    公开(公告)号：US20150287354A1

    公开(公告)日：2015-10-08

    申请号：US14244410

    申请日：2014-04-03

    Applicant: QUALCOMM Mems Technologies, Inc.

    Inventor： Shen-Ge Wang ,  Jian J. Ma

    IPC: G09G3/20 ,  G09G3/34

    CPC classification number: G09G3/2066 ,  G02B5/201 ,  G02B26/001 ,  G09G3/2003 ,  G09G3/2022 ,  G09G3/2051 ,  G09G3/2055 ,  G09G3/2062 ,  G09G3/346 ,  G09G3/3466 ,  G09G5/06 ,  G09G2300/0452 ,  G09G2300/0469 ,  G09G2310/0235 ,  G09G2320/0242 ,  G09G2340/06

    Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for displaying high bit-depth images using a hybrid image dithering method that combines aspect of spatial error diffusion and temporal dithering on display devices including display elements that can display multiple primary colors. Various implementations of the hybrid image dithering method includes a temporal dithering method in which the error associated with selecting the primary color for each sub-frame is diffused to the subsequent sub-frame and diffusing any residual error in the last sub-frame spatially to one or more neighboring pixels

    Abstract translation: 本公开提供了系统，方法和装置，包括在计算机存储介质上编码的计算机程序，用于使用混合图像抖动方法显示高位深度图像，所述混合图像抖动方法将包括可显示的显示元件的显示设备上的空间误差扩散和时间抖动的方面组合 多原色。 混合图像抖动方法的各种实施方式包括时间抖动方法，其中与每个子帧选择原色相关联的错误被扩散到后续子帧，并将空间上的最后子帧中的任何残余误差扩散到一个 或更多相邻像素

    MULTI-STATE INTERFEROMETRIC MODULATOR WITH LARGE STABLE RANGE OF MOTION
    65.
    发明申请
    MULTI-STATE INTERFEROMETRIC MODULATOR WITH LARGE STABLE RANGE OF MOTION 有权
    具有大量稳定运动范围的多状态干涉式调制器

    公开(公告)号：US20150205092A1

    公开(公告)日：2015-07-23

    申请号：US14265193

    申请日：2014-04-29

    Applicant: QUALCOMM MEMS Technologies, Inc.

    Inventor： Teruo Sasagawa ,  Richard Yeh ,  Kostadin Dimitrov Djordjev ,  Hrishikesh Vijaykumar Panchawagh

    IPC: G02B26/00 ,  B81C1/00 ,  G02B1/12

    CPC classification number: G02B26/001 ,  B81B3/00 ,  B81B3/0051 ,  B81B2201/047 ,  B81C1/00134 ,  G02B1/12 ,  G02B26/007 ,  G02B26/0841

    Abstract: This disclosure provides systems, methods and apparatus relating to electromechanical display devices. In one aspect, a multi-stage interferometric modulator (IMOD) can include a movable reflector that can be moved to different positions to produce different reflected colors. The IMOD can include deformable elements that are coupled to a back side of the movable reflector and provide support to the movable reflector. The deformable elements can provide a restoring force that biases the movable reflector to a resting position. The IMOD can include one or more restoring force modifiers that are configured to increase the restoring force when engaged. The restoring force modifiers can be between the movable reflector and the deformable elements such that the deformable elements contact the restoring force modifiers when the movable reflector is displaced to a contacting position.

    Abstract translation: 本公开提供了与机电显示装置有关的系统，方法和装置。 一方面，多级干涉式调制器（IMOD）可以包括可移动的反射器，其可移动到不同的位置以产生不同的反射颜色。 IMOD可以包括耦合到可移动反射器的后侧的可变形元件并且为可移动反射器提供支撑。 可变形元件可以提供将可移动反射器偏置到静止位置的恢复力。 IMOD可以包括一个或多个恢复力修改器，其被配置为当接合时增加恢复力。 恢复力修改器可以在可移动反射器和可变形元件之间，使得当可移动反射器移位到接触位置时，可变形元件接触恢复力修改器。

    Conductive bus structure for interferometric modulator array
    66.
    发明授权
    Conductive bus structure for interferometric modulator array 有权
    用于干涉式调制器阵列的导电总线结构

    公开(公告)号：US09086564B2

    公开(公告)日：2015-07-21

    申请号：US13784491

    申请日：2013-03-04

    Applicant: QUALCOMM MEMS Technologies, Inc.

    Inventor： Clarence Chui ,  Jeffrey B. Sampsell

    IPC: G02B26/00 ,  G09G3/34 ,  B81B3/00

    CPC classification number: G02B26/001 ,  B81B3/0086 ,  G09G3/3466 ,  Y10T29/49117

    Abstract: Embodiments of an interferometric modulator are disclosed having various enhancements and features including a conductive bus. In certain embodiments, the interferometric modulator has a first conductive layer suspended over a second electrode layer. In certain embodiments, a second conductive layer is provided over the first conductive layer. One of the first and/or second conductive buses may further connect to the first electrode layer and/or the second electrode layer. Other disclosed features can be incorporated into embodiments of the interferometric modulator to improve response time, power consumption, and image resolution.

    Abstract translation: 公开了具有包括导电总线的各种增强和特征的干涉式调制器的实施例。 在某些实施例中，干涉式调制器具有悬挂在第二电极层上的第一导电层。 在某些实施例中，在第一导电层上提供第二导电层。 第一和/或第二导电总线之一可以进一步连接到第一电极层和/或第二电极层。 其他公开的特征可并入干涉式调制器的实施例中以改善响应时间，功耗和图像分辨率。

    REGION-DEPENDENT COLOR MAPPING FOR REDUCING VISIBLE ARTIFACTS ON HALFTONED DISPLAYS
    67.
    发明申请
    REGION-DEPENDENT COLOR MAPPING FOR REDUCING VISIBLE ARTIFACTS ON HALFTONED DISPLAYS 审中-公开
    区域相关色彩映射，用于减少显示器上可见的艺术品

    公开(公告)号：US20150103094A1

    公开(公告)日：2015-04-16

    申请号：US14296200

    申请日：2014-06-04

    Applicant: QUALCOMM MEMS Technologies, Inc.

    Inventor： Haitao Xue ,  Manu Parmar ,  Jeho Lee

    IPC: G06T11/00 ,  G09G5/02

    CPC classification number: G06T11/001 ,  G06T2207/20004 ,  G09G5/02 ,  G09G2320/0271 ,  G09G2320/0666 ,  H04N1/6072

    Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for displaying high resolution images with reduced visible halftone noise. In one aspect, an image having a plurality of image pixels is displayed on a display device having a plurality of display pixels, by mapping the tone or color of each input image pixel onto the plurality of display pixels by assigning each display pixel a tone or color value in the color space associated with the display device that is in a neighborhood of the tone or color of each input image pixel and appears to have the same perceptual tone or color value as the image pixel and has a lower visible halftone noise. A size of the neighborhood can be selected based on the color gradient in various portions of the image.

    Abstract translation: 本公开提供了系统，方法和装置，包括在计算机存储介质上编码的计算机程序，用于显示具有减少的可视半色调噪声的高分辨率图像。 在一个方面，通过将每个显示像素分配给多个显示像素，将每个输入图像像素的色调或颜色映射到多个显示像素上，将具有多个图像像素的图像显示在具有多个显示像素的显示装置上 与显示设备相关联的与每个输入图像像素的色调或颜色相邻的颜色空间中的颜色值，并且看起来具有与图像像素相同的感知色调或颜色值，并且具有较低的可视半色调噪声。 可以基于图像的各个部分中的颜色梯度来选择邻域的大小。

    STACKED VIA STRUCTURES AND METHODS OF FABRICATION
    68.
    发明申请
    STACKED VIA STRUCTURES AND METHODS OF FABRICATION 审中-公开
    堆叠通过结构和制造方法

    公开(公告)号：US20150048514A1

    公开(公告)日：2015-02-19

    申请号：US13967243

    申请日：2013-08-14

    Applicant: QUALCOMM MEMS Technologies, Inc.

    Inventor： Hairong Tang ,  Yaoling Pan ,  Tsengyou Syau

    IPC: H01L23/48 ,  H01L21/768

    CPC classification number: H01L23/481 ,  B81B2207/07 ,  B81C1/00095 ,  H01L21/768 ,  H01L21/76801 ,  H01L21/76838 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: This disclosure provides systems, methods and apparatus for a stacked via having a top via structure and a bottom via structure. In one aspect, the bottom via structure includes a bottom dielectric layer and a bottom via extending through the bottom dielectric layer. The bottom via includes a bottom metal formed on the bottom dielectric layer, where the bottom via is substantially filled by a dielectric material. The top via structure includes a top dielectric layer over the bottom metal and a top via extending to a top plane of the bottom via in the top dielectric layer. The top via includes a top metal formed on the top dielectric layer, where the top metal is in electrical contact with the bottom metal at a peripheral area of the bottom via structure.

    Abstract translation: 本公开提供了具有顶部通孔结构和底部通孔结构的堆叠通孔的系统，方法和装置。 一方面，底部通孔结构包括底部电介质层和延伸通过底部电介质层的底部通孔。 底部通孔包括形成在底部电介质层上的底部金属，其中底部通孔基本上由介电材料填充。 顶部通孔结构包括在底部金属上的顶部电介质层和顶部通孔，其在顶部电介质层中延伸到底部通孔的顶部平面。 顶部通孔包括形成在顶部电介质层上的顶部金属，其中顶部金属在底部通孔结构的外围区域与底部金属电接触。

    COMPACT 3-D COPLANAR TRANSMISSION LINES
    70.
    发明申请
    COMPACT 3-D COPLANAR TRANSMISSION LINES 有权
    紧凑型三维共线传输线

    公开(公告)号：US20140361854A1

    公开(公告)日：2014-12-11

    申请号：US13914474

    申请日：2013-06-10

    Applicant: QUALCOMM MEMS Technologies, Inc.

    Inventor： Daeik Daniel Kim ,  David Francis Berdy ,  Jonghae Kim ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Je-Hsiung Jeffrey Lan ,  Robert Paul Mikulka

    IPC: H01P3/02 ,  H05K1/02

    CPC classification number: H01P3/026 ,  H01P3/003 ,  H05K1/0237

    Abstract: This disclosure provides systems, methods and apparatus for a compact 3-D coplanar transmission line (CTL). In one aspect, the CTL has a proximal end and a distal end separated, in a first plane, by a distance D, the first plane being parallel to a layout area of a substrate. The plane is defined by mutually orthogonal axes x and z The CTL provides a conductive path having pathlength L. D is substantially aligned along axis z, L is at least 1.5×D, and the CPW is configured such that at least one third of the pathlength L is disposed along one or more directions having a substantial component orthogonal to the first plane. Less than one third of the pathlength L is disposed in a direction having a substantial component parallel to axis x.

    Abstract translation: 本公开提供了用于紧凑型3-D共面传输线（CTL）的系统，方法和装置。 在一个方面，CTL具有在第一平面中距离D分开的近端和远端，第一平面平行于衬底的布局区域。 平面由相互正交的轴x和z定义。CTL提供具有路径长度L的导电路径.D沿轴线z基本对准，L至少为1.5×D，并且CPW被配置为使得至少三分之一的 路径长度L沿着具有与第一平面正交的实质分量的一个或多个方向布置。 路径长度L的三分之一以具有平行于轴线x的基本分量的方向设置。

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