公开(公告)号：US20120218832A1

公开(公告)日：2012-08-30

申请号：US13359997

申请日：2012-01-27

Applicant: Sang Kwon LEE

Inventor： Sang Kwon LEE

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C7/1096 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1087 ,  G11C11/4096

Abstract: A data transmission circuit includes: a driving voltage generation unit configured to generate a driving voltage having a lower level than an external driving voltage; a switch unit configured to transmit the driving voltage when any one of a write enable signal and a read enable signal is enabled; and a data transmission unit configured to be driven by receiving the driving voltage, transmit a signal of a DQ pad as data in response to the write enable signal, and transmit the data to the DQ pad in response to the read enable signal.

Abstract translation: 数据传输电路包括：驱动电压产生单元，被配置为产生具有比外部驱动电压低的电平的驱动电压; 开关单元，被配置为当使能写入信号和读使能信号中的任何一个被使能时发送驱动电压; 以及数据传输单元，被配置为通过接收驱动电压来驱动，响应于写使能信号，将DQ焊盘的信号作为数据发送，并且响应于读使能信号将数据发送到DQ焊盘。

公开(公告)号：US08189418B2

公开(公告)日：2012-05-29

申请号：US13241885

申请日：2011-09-23

Applicant: Sang Kwon Lee

Inventor： Sang Kwon Lee

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C7/222 ,  G11C7/225 ,  G11C11/40615 ,  G11C11/4076 ,  G11C2211/4065

Abstract: A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal.

Abstract translation: 半导体存储器件的刷新信号产生电路包括一个标志信号发生器，该标志信号发生器响应于刷新信号和一个预充电信号产生一个标志信号;一个时钟使能信号缓冲器，其基于外部时钟使能产生第一和第二缓冲器使能信号 响应于标志信号的信号，以及片选信号缓冲器，其响应于标志信号，基于外部片选信号产生内部片选信号。

公开(公告)号：US20110321081A1

公开(公告)日：2011-12-29

申请号：US13169463

申请日：2011-06-27

Applicant: Sang-kwon LEE ,  Se-jun HAN

Inventor： Sang-kwon LEE ,  Se-jun HAN

IPC: H04N7/00

CPC classification number: H04N21/4753 ,  H04N21/4786 ,  H04N21/4788 ,  H04N21/485

Abstract: An image device, a receiving method of contents, a server, and a providing method of contents are provided. The image device includes: a communication unit which communicates with a server that provides content received from a content provider; a display unit; at least one application execution unit which executes the content; and an application controller which controls the communication unit to receive the content corresponding to a log-in user from the server and displays, on the display unit, reception information indicating reception of the content based on a user ID for the log-in user to be logged in to the image device and a token which matches the user ID to a content ID for the log-in user to be connected to the content provider.

Abstract translation: 提供了图像设备，内容的接收方法，服务器和内容的提供方法。 图像装置包括：通信单元，其与提供从内容提供商接收的内容的服务器进行通信; 显示单元; 执行所述内容的至少一个应用执行单元; 以及应用控制器，其控制所述通信单元从所述服务器接收与登录用户相对应的内容，并且在所述显示单元上，基于所述登录用户的用户ID显示指示接收到所述内容的接收信息， 登录到图像设备和与用户ID匹配的令牌与要连接到内容提供商的登录用户的内容ID。

公开(公告)号：US08041531B2

公开(公告)日：2011-10-18

申请号：US12004786

申请日：2007-12-20

Applicant: Sang Kwon Lee ,  Bong Seok Han

Inventor： Sang Kwon Lee ,  Bong Seok Han

IPC: G11C29/08

CPC classification number: G11C29/06 ,  G11C29/022 ,  G11C29/14 ,  G11C29/46 ,  G11C29/56 ,  G11C29/56012

Abstract: A burn-in test apparatus and a semiconductor device using the same are disclosed. The burn-in test apparatus includes a flag signal generating unit configured to receive an external input signal and an external address externally inputted for a burn-in test and generate a flag signal, and a burn-in test unit configured to receive the flag signal, generate a toggled output enable signal, and drive an input/output line to toggle a signal on the input/output line.

Abstract translation: 公开了一种老化测试装置和使用其的半导体器件。 老化测试装置包括：标志信号生成单元，被配置为接收外部输入信号和从外部输入的用于老化测试的外部地址，并生成标志信号;以及老化测试单元，被配置为接收标志信号 产生切换的输出使能信号，并驱动输入/输出线来切换输入/输出线上的信号。

公开(公告)号：US20110102025A1

公开(公告)日：2011-05-05

申请号：US12825799

申请日：2010-06-29

Applicant: Sang Kwon LEE

Inventor： Sang Kwon LEE

IPC: H03K3/00

CPC classification number: H03K19/00361 ,  H03K19/018585

Abstract: The data output circuit includes a first decoder, a second decoder, a first selective output circuit, a second selective output circuit, and an output driver. The first decoder is configured to generate a pull-up selection signal by decoding a pull-up code. The second decoder is configured to generate a pull-down selection signal by decoding a pull-down code. The first selective output circuit is configured to select and output a voltage level of a pull-up level signal in response to the pull-up selection signal. The second selective output circuit is configured to select and output a voltage level of a pull-down level signal in response to the pull-down selection signal. The output driver is configured to drive output data in response to receiving a pre-pull-up signal and a pre-pull-down signal.

Abstract translation: 数据输出电路包括第一解码器，第二解码器，第一选择输出电路，第二选择输出电路和输出驱动器。 第一解码器被配置为通过解码上拉代码来生成上拉选择信号。 第二解码器被配置为通过解码下拉码产生下拉选择信号。 第一选择输出电路被配置为响应于上拉选择信号来选择和输出上拉电平信号的电压电平。 第二选择输出电路被配置为响应于下拉选择信号选择并输出下拉电平信号的电压电平。 输出驱动器被配置为响应于接收到预上拉信号和预下拉信号来驱动输出数据。

公开(公告)号：US07649801B2

公开(公告)日：2010-01-19

申请号：US11716635

申请日：2007-03-12

Applicant: Sang-Kwon Lee

Inventor： Sang-Kwon Lee

IPC: G11C8/00

CPC classification number: G11C8/10 ,  G11C11/4074 ,  G11C11/4087 ,  G11C2207/2227

Abstract: The present invention relates to a column decoder for low power consumption in a semiconductor memory apparatus. The semiconductor device according to the present invention includes a column select signal decoder, which has a driving voltage input node and uses a driving voltage, for producing a plurality of column select signals by decoding a column select control signal; and a driving voltage supply controller for controlling a supply of the driving voltage to the driving voltage input node.

Abstract translation: 本发明涉及在半导体存储装置中低功耗的列解码器。 根据本发明的半导体器件包括具有驱动电压输入节点并使用驱动电压的列选择信号解码器，用于通过对列选择控制信号进行解码来产生多个列选择信号; 以及用于控制对驱动电压输入节点的驱动电压的供给的驱动电压供给控制器。

公开(公告)号：US07522469B2

公开(公告)日：2009-04-21

申请号：US11823943

申请日：2007-06-29

Applicant: Sang-Kwon Lee

Inventor： Sang-Kwon Lee

IPC: G11C8/00

CPC classification number: G11C7/1072 ,  G11C5/144 ,  G11C7/225 ,  G11C2207/2227

Abstract: A semiconductor memory device includes a clock enable buffer; a clock enable controller; a clock controller; a clock buffer; and a small clock buffer. The clock enable buffer buffers a clock enable signal to provide an internal clock enable signal. The clock enable controller synchronizes the internal clock enable signal with a small clock signal to output a first and a second signal. The clock controller generates a clock buffer enable signal and a small clock buffer enable signal based on the first and the second signals. The clock buffer is driven in response to the clock buffer enable signal and buffers a clock to produce a clock pulse. The small clock buffer is driven in response to the small clock buffer enable signal and buffers the clock to produce the small clock signal.

Abstract translation: 半导体存储器件包括时钟使能缓冲器; 时钟使能控制器; 时钟控制器 一个时钟缓冲器 和一个小时钟缓冲区。 时钟使能缓冲器缓冲时钟使能信号以提供内部时钟使能信号。 时钟使能控制器将内部时钟使能信号与小时钟信号同步，以输出第一和第二信号。 时钟控制器基于第一和第二信号产生时钟缓冲器使能信号和小时钟缓冲器使能信号。 响应于时钟缓冲器使能信号驱动时钟缓冲器，并缓冲时钟以产生时钟脉冲。 响应于小时钟缓冲器使能信号驱动小时钟缓冲器，缓冲时钟以产生小时钟信号。

公开(公告)号：US20080291761A1

公开(公告)日：2008-11-27

申请号：US12004786

申请日：2007-12-20

Applicant: Sang Kwon Lee ,  Bong Seok Han

Inventor： Sang Kwon Lee ,  Bong Seok Han

IPC: G11C29/08

CPC classification number: G11C29/06 ,  G11C29/022 ,  G11C29/14 ,  G11C29/46 ,  G11C29/56 ,  G11C29/56012

Abstract: A burn-in test apparatus and a semiconductor device using the same are disclosed. The burn-in test apparatus includes a flag signal generating unit configured to receive an external input signal and an external address externally inputted for a burn-in test and generate a flag signal, and a burn-in test unit configured to receive the flag signal, generate a toggled output enable signal, and drive an input/output line to toggle a signal on the input/output line.

Abstract translation: 公开了一种老化测试装置和使用其的半导体器件。 老化测试装置包括：标志信号生成单元，被配置为接收外部输入信号和外部输入的用于老化测试的外部地址，并生成标志信号;以及老化测试单元，被配置为接收标志信号 产生切换的输出使能信号，并驱动输入/输出线来切换输入/输出线上的信号。

公开(公告)号：US20080208976A1

公开(公告)日：2008-08-28

申请号：US11872181

申请日：2007-10-15

Applicant: Akhil CHAPALAMADUGU ,  Sang-kwon LEE ,  Guanhua ZHANG ,  Hyok-Sung CHOI

Inventor： Akhil CHAPALAMADUGU ,  Sang-kwon LEE ,  Guanhua ZHANG ,  Hyok-Sung CHOI

IPC: G06F15/16

CPC classification number: H04L67/104 ,  H04L67/1076 ,  H04L67/1085 ,  H04L67/322 ,  H04L67/325 ,  H04L69/40

Abstract: A system and method of providing quality of service (QoS)-enabled digital content in peer-to-peer (P2P) networks are provided. The QoS-enabled service system on the P2P network includes: a service provider capable of providing digital content; one or more user nodes receiving digital content from the service provider; one or more donor nodes lending resources for providing digital content; and a supernode receiving information on user nodes and donor nodes, and a copy of digital content from the service provider, allowing the exchange of digital content among the user nodes through P2P networking, and when at least one user node experiences a P2P networking error during the exchange of the digital content, arranging for a predetermined number of donor nodes from among the one or more donor nodes to join the P2P networking. According to the system and method, even when the function of a peer does not normally work on a P2P network, a donor as a replacement of the peer is utilized, thereby providing QoS-enabled digital content to a user requesting the digital content.

Abstract translation: 提供了一种在对等（P2P）网络中提供服务质量（QoS）的数字内容的系统和方法。 P2P网络上支持QoS的业务系统包括：能够提供数字内容的业务提供者; 从服务提供商接收数字内容的一个或多个用户节点; 一个或多个捐赠节点为提供数字内容提供资源; 以及从用户节点和供体节点接收信息的超级节点，以及来自服务提供商的数字内容的副本，允许通过P2P网络在用户节点之间交换数字内容，并且当至少一个用户节点在P2P网络中经历P2P网络错误时 数字内容的交换，从一个或多个捐赠者节点安排预定数量的捐赠者节点以加入P2P网络。 根据该系统和方法，即使对等体的功能在P2P网络上不能正常工作，也可以利用作为对等体的替代者的供体，从而向请求数字内容的用户提供支持QoS的数字内容。

公开(公告)号：US20080080290A1

公开(公告)日：2008-04-03

申请号：US11823943

申请日：2007-06-29

Applicant: Sang-Kwon Lee

Inventor： Sang-Kwon Lee

IPC: G11C11/4193

CPC classification number: G11C7/1072 ,  G11C5/144 ,  G11C7/225 ,  G11C2207/2227

Abstract: A semiconductor memory device includes a clock enable buffer; a clock enable controller; a clock controller; a clock buffer; and a small clock buffer. The clock enable buffer buffers a clock enable signal to provide an internal clock enable signal. The clock enable controller synchronizes the internal clock enable signal with a small clock signal to output a first and a second signal. The clock controller generates a clock buffer enable signal and a small clock buffer enable signal based on the first and the second signals. The clock buffer is driven in response to the clock buffer enable signal and buffers a clock to produce a clock pulse. The small clock buffer is driven in response to the small clock buffer enable signal and buffers the clock to produce the small clock signal.

Abstract translation: 半导体存储器件包括时钟使能缓冲器; 时钟使能控制器; 时钟控制器 一个时钟缓冲器 和一个小时钟缓冲区。 时钟使能缓冲器缓冲时钟使能信号以提供内部时钟使能信号。 时钟使能控制器将内部时钟使能信号与小时钟信号同步，以输出第一和第二信号。 时钟控制器基于第一和第二信号产生时钟缓冲器使能信号和小时钟缓冲器使能信号。 响应于时钟缓冲器使能信号驱动时钟缓冲器，并缓冲时钟以产生时钟脉冲。 响应于小时钟缓冲器使能信号驱动小时钟缓冲器，缓冲时钟以产生小时钟信号。