公开(公告)号：US20090230953A1

公开(公告)日：2009-09-17

申请号：US12403992

申请日：2009-03-13

Applicant: Seong-Jae Lee

Inventor： Seong-Jae Lee

IPC: G01R33/025 ,  G01L3/10

CPC classification number: G01L3/102 ,  G01R33/07

Abstract: The present invention involves a method and apparatus for canceling the effects of magnetic field noise in a torque sensor by placing three sets of magnetic field sensors around a shaft, the first set of field sensors being placed in the central region of the shaft and the second and third sets of field sensors being placed on the right side and left side of the field sensors placed at the central region, respectively. A torque-induced magnetic field is not cancelled with this arrangement of field sensors but a magnetic near field from a near field source is cancelled.

Abstract translation: 本发明涉及一种用于通过将三组磁场传感器放置在轴周围来消除扭矩传感器中的磁场噪声的影响的方法和装置，第一组场传感器被放置在轴的中心区域中，而第二组 并且第三组场传感器分别放置在放置在中心区域的场传感器的右侧和左侧。 通过这种现场传感器的布置，扭矩感应磁场不被抵消，而来自近场源的磁场近场被取消。

公开(公告)号：US07566642B2

公开(公告)日：2009-07-28

申请号：US11188076

申请日：2005-07-22

Applicant: Yark Yeon Kim ,  Moon Gyu Jang ,  Jae Heon Shin ,  Seong Jae Lee

Inventor： Yark Yeon Kim ,  Moon Gyu Jang ,  Jae Heon Shin ,  Seong Jae Lee

IPC: H01L21/44

CPC classification number: H01L29/665 ,  H01L21/2252 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/28537 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7839

Abstract: An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on the channel region and has a gate dielectric layer on its interface with respect to the silicon layer. The double layer is formed as a source/drain that has the channel region interposed on the silicon layer.

Abstract translation: 提供了n型SBTT及其制造方法。 SBTT包括硅层，栅极，具有稀土金属硅化物层和过渡金属硅化物层的双层。 硅层具有沟道区。 栅极以重叠的方式形成在沟道区上，并且在其相对于硅层的界面上具有栅极介电层。 双层形成为具有介于硅层之间的沟道区的源极/漏极。

公开(公告)号：US07539119B2

公开(公告)日：2009-05-26

申请号：US11296935

申请日：2005-12-07

Applicant: Jong Hyurk Park ,  Seong Jae Lee

Inventor： Jong Hyurk Park ,  Seong Jae Lee

IPC: G11B7/00

CPC classification number: G11B9/04

Abstract: Provided is a data storage apparatus using current switching in a metal oxide layer. The data storage apparatus includes a substrate; a lower electrode layer disposed on the substrate; a metal oxide layer disposed on the lower electrode layer; a probe tip disposed on the metal oxide layer opposite the lower electrode layer and for scanning a local region of the metal oxide layer in units of nanometer, wherein the probe tip applies a write voltage to the local region of the metal oxide layer so that the resistance of the local region is sharply changed until a resistive state of the local region is switched from a first state to a second state or measures current flowing through the local region according to the resistive state and reads data stored in the local region; a driver for transferring the position of the probe tip to the local region of the metal oxide layer; and a controller for controlling the probe tip and the driver.

Abstract translation: 提供了一种在金属氧化物层中使用电流切换的数据存储装置。 数据存储装置包括：基板; 设置在所述基板上的下电极层; 设置在下电极层上的金属氧化物层; 探针尖端，设置在与下电极层相对的金属氧化物层上，用于以纳米单位扫描金属氧化物层的局部区域，其中探针尖端向金属氧化物层的局部区域施加写入电压，使得 局部区域的电阻急剧变化，直到局部区域的电阻状态从第一状态切换到第二状态，或根据电阻状态测量流过局部区域的电流，并读取存储在局部区域中的数据; 用于将探针头的位置转移到金属氧化物层的局部区域的驱动器; 以及用于控制探针尖端和驾驶员的控制器。

公开(公告)号：US07537883B2

公开(公告)日：2009-05-26

申请号：US11447820

申请日：2006-06-06

Applicant: Han Young Yu ,  In Bok Baek ,  Chang Geun Ahn ,  Ki Ju Im ,  Jong Heon Yang ,  Ung Hwan Pi ,  Min Ki Ryu ,  Chan Woo Park ,  Sung Yool Choi ,  Seong Jae Lee

Inventor： Han Young Yu ,  In Bok Baek ,  Chang Geun Ahn ,  Ki Ju Im ,  Jong Heon Yang ,  Ung Hwan Pi ,  Min Ki Ryu ,  Chan Woo Park ,  Sung Yool Choi ,  Seong Jae Lee

IPC: G03F7/00 ,  H01L51/40 ,  C25D5/18

CPC classification number: H01L51/105 ,  B82Y10/00 ,  H01L51/0023 ,  H01L51/0595

Abstract: Provided is a method of manufacturing a nano size-gap electrode device. The method includes the steps of: disposing a floated nano structure on a semiconductor layer; forming a mask layer having at least one opening pattern to intersect the nano structure; and depositing a metal on the semiconductor layer exposed through the opening pattern to form an electrode, such that a nano size-gap is provided under the nano structure by the nano structure.

Abstract translation: 提供一种制造纳米尺寸间隙电极器件的方法。 该方法包括以下步骤：在半导体层上设置漂浮的纳米结构; 形成具有至少一个开口图案以与纳米结构相交的掩模层; 以及在通过所述开口图案暴露的所述半导体层上沉积金属以形成电极，使得通过所述纳米结构在所述纳米结构下方提供纳米尺寸间隙。

公开(公告)号：US20070152791A1

公开(公告)日：2007-07-05

申请号：US11306571

申请日：2006-01-03

Applicant: Seong-Jae Lee ,  Dennis O'Neel

Inventor： Seong-Jae Lee ,  Dennis O'Neel

IPC: H01F7/02

CPC classification number: B03C1/288 ,  B03C2201/18

Abstract: A magnetic array having a collar with a plurality of magnets mounted to the inner surface of the collar. The magnets are positioned in a spaced alignment around the collar with all having the same polarity facing toward the center of the collar. Shielding is used to control and/or contain the direction of the magnetic force and the array is covered with a plastic coating.

Abstract translation: 一种磁性阵列，其具有安装在所述轴环的内表面上的多个磁体的轴环。 磁体以围绕套环的间隔对齐的方式定位，其全部具有面向轴环中心的相同极性。 屏蔽用于控制和/或包含磁力的方向，并且阵列被塑料涂层覆盖。

公开(公告)号：US07098092B2

公开(公告)日：2006-08-29

申请号：US10691852

申请日：2003-10-22

Applicant: Tae Woong Kang ,  Seong Jae Lee

Inventor： Tae Woong Kang ,  Seong Jae Lee

IPC: H01L21/84

CPC classification number: B82Y10/00 ,  H01L29/66439 ,  H01L29/7613

Abstract: Disclosed is to a single electron device, a method of manufacturing the same, and a method of simultaneously manufacturing a single electron device and an MOS transistor. Accordingly, the single electron device of the present invention comprises, on a substrate, semiconductor layers in which a source region and a drain region spaced a predetermined distance apart are formed, hemisphere-type silicon layer formed between the semiconductor layers as an active layer, the hemisphere-type silicon layer having a plurality of electron islands, a gate insulating layer formed on a top surface of the entire structure, and a gate electrode formed on the gate insulating layer in order to apply voltage to the active layer.

Abstract translation: 公开了单电子器件及其制造方法，以及同时制造单电子器件和MOS晶体管的方法。 因此，本发明的单电子器件在衬底上包括形成间隔开预定距离的源区和漏区的半导体层，形成在作为有源层的半导体层之间的半球型硅层， 具有多个电子岛的半球型硅层，形成在整个结构的顶表面上的栅极绝缘层，以及形成在栅极绝缘层上的栅电极，以向该有源层施加电压。

公开(公告)号：US06770534B2

公开(公告)日：2004-08-03

申请号：US10617183

申请日：2003-07-11

Applicant: Wonju Cho ,  Seong Jae Lee ,  Kyoung Wan Park

Inventor： Wonju Cho ,  Seong Jae Lee ,  Kyoung Wan Park

IPC: H01L21336

CPC classification number: H01L29/78642 ,  H01L27/1203 ,  Y10S977/712 ,  Y10S977/721 ,  Y10S977/723 ,  Y10S977/887

Abstract: The present invention relates to an ultra small size vertical MOSFET device having a vertical channel and a source/drain structure and a method for the manufacture thereof by using a silicon on insulator (SOI) substrate. To begin with, a first silicon conductive layer is formed by doping an impurity of a high concentration into a first single crystal silicon layer. Thereafter, a second single crystal silicon layer with the impurity of a low concentration and a second silicon conductive layer with the impurity of the high concentration are formed on the first silicon conductive layer. The second single crystal silicon layer and the second silicon conductive layer are vertically patterned into a predetermined configuration. Subsequently, a gate insulating layer is formed on entire surface. Then, an annealing process is carried out to diffuse the impurities in the first silicon conductive layer and the second silicon conductive layer into the second single crystal layer, thereby forming a source contact, a drain contact and a vertical channel. Finally, a gate electrode is formed on side walls of the vertical channel.

Abstract translation: 本发明涉及具有垂直沟道和源极/漏极结构的超小尺寸垂直MOSFET器件及其通过使用绝缘体上硅（SOI）衬底制造的方法。 首先，通过将高浓度的杂质掺杂到第一单晶硅层中来形成第一硅导电层。 此后，在第一硅导电层上形成具有低浓度杂质的第二单晶硅层和具有高浓度杂质的第二硅导电层。 将第二单晶硅层和第二硅导电层垂直图案化成预定构造。 随后，在整个表面上形成栅极绝缘层。 然后，进行退火处理，以将第一硅导电层和第二硅导电层中的杂质扩散到第二单晶层中，从而形成源极接触，漏极接触和垂直沟道。 最后，在垂直通道的侧壁上形成栅电极。

公开(公告)号：US06680663B1

公开(公告)日：2004-01-20

申请号：US09814640

申请日：2001-03-22

Applicant: Seong-Jae Lee ,  David Jiles ,  Karl A. Gschneidner, Jr. ,  Vitalij Pecharsky

Inventor： Seong-Jae Lee ,  David Jiles ,  Karl A. Gschneidner, Jr. ,  Vitalij Pecharsky

IPC: H01F702

CPC classification number: G01R33/383 ,  F25B2321/002 ,  H01F7/0278

Abstract: A permanent magnet structure for maximizing the flux density per weight of magnetic material comprising a hollow body flux source for generating a magnetic field in the central gap of the hollow body, the magnetic field having a flux density greater than the residual flux density of the hollow body flux source. The hollow body flux source has a generally elliptic-shape, defined by unequal major and minor axis. These elliptic-shaped permanent magnet structures exhibit a higher flux density at the center gap while minimizing the amount of magnetic material used. Inserts of soft magnetic material proximate the central gap, and a shell of soft magnetic material surrounding the hollow body can further increase the strength of the magnetic field in the central gap by reducing the magnetic flux leakage and focusing the flux density lines in the central gap.

Abstract translation: 一种永磁体结构，用于使每个重量的磁性材料的磁通密度最大化，包括用于在中空体的中心间隙中产生磁场的中空体磁通源，该磁场的磁通密度大于空心体的剩余通量密度 身体通量来源。 中空体通量源具有大致椭圆形，由不等长的主轴和短轴限定。 这些椭圆形永磁体结构在中心间隙处表现出较高的通量密度，同时最小化使用的磁性材料的量。 靠近中心间隙的软磁性材料的插入件和围绕中空体的软磁性材料的壳体可以通过减小磁通量泄漏并将中心间隙中的磁通密度线聚焦，来进一步增加中心间隙中的磁场强度 。

公开(公告)号：US5872372A

公开(公告)日：1999-02-16

申请号：US712410

申请日：1996-09-11

Applicant: Seong-Jae Lee ,  Kyoung-Wan Park ,  Min-Cheol Shin

Inventor： Seong-Jae Lee ,  Kyoung-Wan Park ,  Min-Cheol Shin

IPC: H01L41/107 ,  H01L29/786 ,  H01L29/84 ,  H01L41/08 ,  H01L29/82

CPC classification number: H01L29/7849 ,  H01L29/84 ,  H01L29/78 ,  H01L29/786

Abstract: A thin film transistor is disclosed comprising a piezoelectric film formed on a piezoresistive body of an ultra thin film and a gate electrode formed on the piezoelectric film. Due to the force generated from the piezoelectric film by an electric field generated according to the strength of a voltage applied to the gate electrode, a pressure is applied on the piezoresistive body to vary the resistance of the piezoresistive body. Thus, the quantity of current that flows from a source terminal through the piezoresistive channel to a drain terminal can be controlled. Since the piezoresistive body can be formed on a plane, a thin film transistor with a three-dimensional structure can be manufactured.

Abstract translation: 公开了一种薄膜晶体管，其包括形成在超薄膜的压阻体上的压电膜和形成在压电膜上的栅电极。 由于通过根据施加到栅电极的电压的强度而产生的电场由压电膜产生的力，对压阻体施加压力以改变压阻体的电阻。 因此，可以控制从源极端子通过压阻通道流向漏极端子的电流量。 由于可以在平面上形成压阻体，因此可以制造具有三维结构的薄膜晶体管。

公开(公告)号：US09617051B2

公开(公告)日：2017-04-11

申请号：US14322316

申请日：2014-07-02

Applicant: Jeong-Min Lee ,  Seong-Jae Lee

Inventor： Jeong-Min Lee ,  Seong-Jae Lee

IPC: B65D51/28 ,  B65D47/08 ,  B65D47/12 ,  B65D47/20 ,  B65D47/24 ,  B65D47/30 ,  B65D49/04 ,  B65D51/00 ,  B05B11/00 ,  B65D41/50

CPC classification number: B65D51/2857 ,  B05B11/3047 ,  B65D41/505 ,  B65D47/0838 ,  B65D47/12 ,  B65D47/127 ,  B65D47/2006 ,  B65D47/243 ,  B65D47/305 ,  B65D49/04 ,  B65D51/002 ,  B65D51/2828 ,  B65D51/2835 ,  B65D51/2842 ,  B65D51/2864 ,  B65D51/2892

Abstract: A bottle cap that is an apparatus for containing heterogeneous materials, applied in the discharge direction of materials in a container, comprises: a main body coupled to a bottle neck; and a containing unit assembled inside the main body with a storage space. An activated unit is assembled in the center of the upper support unit of the main body. An activation unit for downward movement is coupled to the activated unit so that the activated unit may move downward by a separate activation unit. An opening/closing unit is coupled with the lower part of the activated unit with the above structure in order to seal an opening/closing hole of the storage space.