公开(公告)号：US08435878B2

公开(公告)日：2013-05-07

申请号：US12754917

申请日：2010-04-06

Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Yanfeng Wang

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Yanfeng Wang

IPC: H01L21/00

CPC classification number: H01L29/42368 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/66477

Abstract: A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device.

Abstract translation: 一种用于形成场效应晶体管（FET）器件的方法，包括在衬底上形成电介质层，在电介质层上形成第一金属层，去除第一金属层的一部分以露出电介质层的一部分，形成 在所述电介质层和所述第一金属层上的第二金属层，以及去除所述第一金属层和所述第二金属层的一部分，以限定第一FET器件和第二FET器件之间的边界区域。

公开(公告)号：US20130093018A1

公开(公告)日：2013-04-18

申请号：US13272349

申请日：2011-10-13

Applicant: Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

Inventor： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/2822 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A method includes providing a wafer that has a semiconductor layer having an insulator layer disposed on the semiconductor layer. The insulator layer has openings made therein to expose a surface of the semiconductor layer, where each opening corresponds to a location of what will become a transistor channel in the semiconductor layer disposed beneath a gate stack. The method further includes depositing a high dielectric constant gate insulator layer so as to cover the exposed surface of the semiconductor layer and sidewalls of the insulator layer; depositing a gate metal layer that overlies the high dielectric constant gate insulator layer; and implanting Carbon through the gate metal layer and the underlying high dielectric constant gate insulator layer so as to form in an upper portion of the semiconductor layer a Carbon-implanted region having a concentration of Carbon selected to establish a voltage threshold of the transistor.

Abstract translation: 一种方法包括提供具有设置在半导体层上的绝缘体层的半导体层的晶片。 绝缘体层具有在其中形成的开口以暴露半导体层的表面，其中每个开口对应于在栅叠层下方的半导体层中将成为晶体管沟道的位置。 该方法还包括沉积高介电常数栅极绝缘体层以覆盖半导体层的暴露表面和绝缘体层的侧壁; 沉积覆盖在高介电常数栅极绝缘体层上的栅极金属层; 以及通过栅极金属层和下面的高介电常数栅极绝缘体层注入碳以便在半导体层的上部形成具有选定的碳浓度的碳注入区域，以建立晶体管的电压阈值。

公开(公告)号：US08354720B2

公开(公告)日：2013-01-15

申请号：US13529558

申请日：2012-06-21

Applicant: Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

Inventor： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

IPC: H01L27/12

CPC classification number: H01L29/1054 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78687

Abstract: A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a plurality of spacers disposed on laterally opposing sides of the gate stack; source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions; and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape.

Abstract translation: 半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; 设置在所述栅极堆叠的横向相对侧上的多个间隔件; 邻近间隔物的源极和漏极区域以及位于栅极堆叠下方并设置在源极和漏极区域之间的沟道区域; 以及位于所述沟道区域的下方并嵌入在所述半导体衬底内的应力器，所述嵌入式应力器由三角形形成。

公开(公告)号：US20120326126A1

公开(公告)日：2012-12-27

申请号：US13167570

申请日：2011-06-23

Applicant: Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han ,  James Bowler Hannon ,  Katherine L. Saenger ,  George Stojan Tulevski

Inventor： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han ,  James Bowler Hannon ,  Katherine L. Saenger ,  George Stojan Tulevski

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/06 ,  H01L29/16 ,  B82Y40/00 ,  B82Y99/00

CPC classification number: H01L29/7781 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/1075 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0023 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/055

Abstract: Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

Abstract translation: 提供具有基于纳米材料的通道（例如，碳纳米管或石墨烯通道）的晶体管器件及其制造技术。 一方面，提供一种晶体管器件。 晶体管器件包括衬底; 衬底上的绝缘体; 嵌入绝缘体中的局部底栅，其中栅极的顶表面与绝缘体的表面基本共面; 底栅上的局部栅极电介质; 在所述局部栅极电介质的至少一部分上的碳基纳米结构材料，其中所述碳基纳米结构材料的一部分用作所述器件的通道; 并且导电源极和漏极接触到用作器件的源极和漏极区域的沟道的相对侧上的碳基纳米结构材料的一个或多个部分。

公开(公告)号：US20120306026A1

公开(公告)日：2012-12-06

申请号：US13118750

申请日：2011-05-31

Applicant: Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

Inventor： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A tungsten barrier portion is employed in a replacement gate structure to block diffusion of material from a metal portion to a work function material portion. The tungsten barrier portion effectively functions as a diffusion barrier layer between the metal portion and the work function material portion so that the composition of the work function material portion is unaffected by anneal and/or usage of the field effect transistor including the replacement gate structure. Thus, the threshold voltage of the field effect transistor can remain stable throughout processing steps and usage in the field.

Abstract translation: 在替代栅极结构中采用钨阻挡部分以阻止材料从金属部分扩散到功函件材料部分。 钨阻挡部分有效地用作金属部分和功函材料部分之间的扩散阻挡层，使得功函数材料部分的组成不受包括替换栅极结构的场效应晶体管的退火和/或使用的影响。 因此，场效应晶体管的阈值电压可以在整个处理步骤和现场使用中保持稳定。

公开(公告)号：US20120292602A1

公开(公告)日：2012-11-22

申请号：US13111615

申请日：2011-05-19

Applicant: DECHAO GUO ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

Inventor： DECHAO GUO ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC: H01L51/10 ,  H01L51/40

CPC classification number: H01L29/66515 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0045 ,  H01L51/0048 ,  H01L51/0525 ,  H01L51/0545

Abstract: A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack comprising a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.

Abstract translation: 一种用于器件制造的器件和方法包括在电介质衬底中形成掩埋栅极电极，并且在掩埋栅电极上图案化包括高介电常数层，碳基半导电层和保护层的堆叠。 在叠层上形成的绝缘介电层被打开以在与堆叠相邻的区域中限定凹陷。 蚀刻凹槽以形成空腔并去除高介电常数层的一部分以暴露在掩埋栅电极的相对侧上的碳基半导体层。 导电材料沉积在空腔中以形成自对准的源区和漏区。

公开(公告)号：US20120286244A1

公开(公告)日：2012-11-15

申请号：US13104591

申请日：2011-05-10

Applicant: Hsin-Ying Chiu ,  Shu-Jen Han ,  Hareem Tariq Maune

Inventor： Hsin-Ying Chiu ,  Shu-Jen Han ,  Hareem Tariq Maune

IPC: H01L51/30 ,  H01L51/40

CPC classification number: H01L29/7781 ,  B82Y10/00 ,  H01L29/42364 ,  H01L29/66462 ,  H01L51/0048 ,  H01L51/0529 ,  H01L51/0558

Abstract: Carbon transistor devices having channels formed from carbon nanostructures, such as carbon nanotubes or graphene, and having charged monolayers to reduce parasitic resistance in un-gated regions of the channels, and methods for fabricating carbon transistor devices having charged monolayers to reduce parasitic resistance. For example, a carbon field effect transistor includes a channel comprising a carbon nanostructure formed on an insulating layer, a gate structure formed on the channel, a monolayer of DNA conformally covering the gate structure and a portion of the channel adjacent the gate structure, an insulating spacer conformally formed on the monolayer of DNA, and source and drain contacts connected by the channel

Abstract translation: 具有由诸如碳纳米管或石墨烯之类的碳纳米结构形成的通道的碳晶体管器件以及具有带电单层以降低通道的未门控区域中的寄生电阻的方法以及用于制造具有带电单层以降低寄生电阻的碳晶体管器件的方法。 例如，碳场效应晶体管包括通道，其包括在绝缘层上形成的碳纳米结构，在沟道上形成的栅极结构，保形地覆盖栅极结构的DNA单层和邻近栅极结构的沟道的一部分， 在DNA的单层上保形地形成绝缘垫片，以及由通道连接的源极和漏极触点

公开(公告)号：US20120248535A1

公开(公告)日：2012-10-04

申请号：US13487473

申请日：2012-06-04

Applicant: Cheng-Wei Cheng ,  Shu-Jen Han ,  Kuen-Ting Shiu

Inventor： Cheng-Wei Cheng ,  Shu-Jen Han ,  Kuen-Ting Shiu

IPC: H01L29/786

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/454 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/78681

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer.

Abstract translation: 场效应晶体管（FET），包括FET的集成电路（IC）芯片，以及形成FET和IC的方法。 FET位置限定在分层半导体晶片上。 分层半导体晶片优选地包括III-V半导体表面层，例如砷化镓（GaAs）和掩埋层，例如砷化铝（AlAs）。 掩埋层的一部分至少在FET源极/漏极区下面被转换为电介质材料，例如氧化铝（AlO）。 转换的电介质材料可以在FET下完全延伸。 源极/漏极触点形成在掩埋层中的电介质材料上方的FET上。

公开(公告)号：US20120132913A1

公开(公告)日：2012-05-31

申请号：US12955203

申请日：2010-11-29

Applicant: Kuen-Ting Shiu ,  Dechao Guo ,  Shu-Jen Han ,  Edward W. Kiewra ,  Masaharu Kobayashi

Inventor： Kuen-Ting Shiu ,  Dechao Guo ,  Shu-Jen Han ,  Edward W. Kiewra ,  Masaharu Kobayashi

IPC: H01L29/78 ,  H01L21/20

CPC classification number: H01L29/0603 ,  H01L21/28158 ,  H01L21/28264 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/78 ,  H01L29/7833

Abstract: The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.

Abstract translation: 本公开通过在单晶III-V化合物半导体材料层的上表面上提供薄的晶体中间层来减少并且在一些情况下消除III-V族化合物半导体材料中的界面态的密度，以保护单晶III-V化合物半导体材料层的结晶度 单晶III-V化合物半导体材料层的表面原子在进一步处理结构之前。

公开(公告)号：US08138547B2

公开(公告)日：2012-03-20

申请号：US12548005

申请日：2009-08-26

Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L21/84 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/7839 ,  H01L29/78624

Abstract: A semiconductor device is disclosed that includes a silicon-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a deep source region are formed in the semiconductor layer. A first metal-semiconductor alloy contact layer is formed using tilted metal formation at an angle tilted towards the source extension region, such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate from the source side, as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region. A second metal-semiconductor alloy contact is formed located on the first metal-semiconductor layer on each of the source extension region and drain extension region.

Abstract translation: 公开了一种半导体器件，其包括绝缘体上硅衬底，其包括掩埋绝缘体层和上覆半导体层。 在半导体层中形成源延伸和漏扩展区。 在半导体层中形成深漏极区域和深源极区域。 第一金属 - 半导体合金接触层使用倾斜的金属形成，以朝向源延伸区域倾斜的角度形成，使得源极延伸区域具有金属 - 半导体合金接触件，其从源极侧邻接衬底，作为肖特基接触 并且栅极屏蔽金属沉积物抵靠深漏极区域。 在源极延伸区域和漏极延伸区域中的每一个上，在第一金属 - 半导体层上形成第二金属 - 半导体合金接触。