公开(公告)号：US20100308333A1

公开(公告)日：2010-12-09

申请号：US12560652

申请日：2009-09-16

申请人： Hyeong-Suk YOO ,  Ho-Jun LEE ,  Sung-ryul KIM ,  O-Sung SEO ,  Hong-Kee CHIN

发明人： Hyeong-Suk YOO ,  Ho-Jun LEE ,  Sung-ryul KIM ,  O-Sung SEO ,  Hong-Kee CHIN

IPC分类号： H01L33/00 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1248

摘要： A method of manufacturing a thin film transistor capable of simplifying a substrate structure and a manufacturing process is disclosed. The method of manufacturing a thin film transistor array substrate comprising a three mask process. The 3 mask process comprising, forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming a first, second, and third passivation film successively on the substrate. Over the above multi-layers of the passivation film forming a first photoresist pattern comprising a first portion formed on part of the drain electrode and on the pixel region, and a second portion wherein, the second portion thicker than the first portion, and then patterning the third passivation film using the first photoresist pattern, forming a second photoresist pattern by removing the first portion of the first photoresist pattern, forming a transparent electrode film on the substrate, removing the second photoresist pattern and the transparent electrode film disposed on the second photoresist pattern; and forming a transparent electrode pattern on the second passivation layer.

摘要翻译： 公开了一种能够简化衬底结构和制造工艺的制造薄膜晶体管的方法。 制造包括三掩模工艺的薄膜晶体管阵列基板的方法。 3掩模工艺包括：在衬底上形成栅极图案，在衬底上形成栅极绝缘膜，在衬底上形成源极/漏极图案和半导体图案，在第一，第二和第三钝化膜上依次形成第一，第二和第三钝化膜 基质。 在上述多层钝化膜上形成第一光致抗蚀剂图案，该第一光致抗蚀剂图案包括形成在漏电极的一部分上和在像素区域上的第一部分，以及第二部分，其中第二部分比第一部分厚， 使用第一光致抗蚀剂图案的第三钝化膜，通过去除第一光致抗蚀剂图案的第一部分形成第二光致抗蚀剂图案，在基板上形成透明电极膜，去除第二光致抗蚀剂图案和设置在第二光致抗蚀剂上的透明电极膜 模式; 以及在所述第二钝化层上形成透明电极图案。

公开(公告)号：US07474588B2

公开(公告)日：2009-01-06

申请号：US11755165

申请日：2007-05-30

申请人： Sung-Ryul Kim

发明人： Sung-Ryul Kim

IPC分类号： G11C8/18

CPC分类号： G11C7/1051 ,  G11C7/1012 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

摘要： A data output circuit for an integrated circuit memory device includes a control circuit that is configured to generate a plurality of clock signals responsive to at least a portion of a memory column address, and a multiplexer circuit that is configured to output memory data received on input terminals thereof onto an output terminal responsive to selective invocation of the plurality of clock signals. The clock signals are invoked in an order based on the at least a portion of the memory column address.

摘要翻译： 用于集成电路存储器件的数据输出电路包括一个控制电路，该控制电路被配置为响应于存储器列地址的至少一部分产生多个时钟信号;以及多路复用器电路，被配置为输出在输入端上接收的存储器数据 其端子响应于选择性地调用多个时钟信号而输出到输出端上。 基于存储器列地址的至少一部分的顺序调用时钟信号。

公开(公告)号：US07465496B2

公开(公告)日：2008-12-16

申请号：US10552461

申请日：2004-04-03

申请人： Jang-Woo Park ,  Sung-Ryul Kim ,  Su-Mi Choi

发明人： Jang-Woo Park ,  Sung-Ryul Kim ,  Su-Mi Choi

IPC分类号： B32B5/66

CPC分类号： C08L51/08 ,  C08F283/10 ,  C08F290/06 ,  C09D5/32 ,  C09D151/08 ,  C09J7/22 ,  Y10T428/2991 ,  Y10T428/2993 ,  Y10T428/2995 ,  Y10T428/2996 ,  Y10T428/2998 ,  C08L2666/02

摘要： Disclosed is a novel concept of infrared blocking powder, that is to say, indium antimony tin oxide (IATO), which is produced by mixing indium (In), antimony (Sb), and tin (Sn) in a predetermined mixing ratio, and co-precipitating a mixture in solvent. Additionally, the present invention provides infrared blocking solution and infrared blocking material using the infrared blocking powder, which allow visible rays to transmit therethrough but effectively block near-infrared rays acting as thermic rays.

摘要翻译： 公开了一种红外阻挡粉末的新概念，也就是说，通过以预定的混合比混合铟（In），锑（Sb）和锡（Sn）制备的铟锑锡氧化物（IATO），以及 在溶剂中共沉淀混合物。 此外，本发明提供使用红外阻挡粉末的红外阻挡溶液和红外阻挡材料，其允许可见光透射通过，但有效地阻挡作为热光线的近红外线。

公开(公告)号：US20080202689A1

公开(公告)日：2008-08-28

申请号：US12113901

申请日：2008-05-01

申请人： Sung Ryul Kim

发明人： Sung Ryul Kim

IPC分类号： H01L21/306 ,  C23C16/44

CPC分类号： H01J37/32724 ,  H01J37/32477 ,  H01J37/32522 ,  H01J37/32568

摘要： A plasma processing apparatus includes: a chamber; an insulating member disposed in an upper portion of the chamber; a ground electrode formed at a side wall of the chamber, a ground potential being applied to the ground electrode; and a lower electrode disposed in a lower portion of the chamber, a substrate being placed on the lower electrode, wherein the lower electrode is divided into a plurality of electrodes.According to an aspect of the present invention, particles accumulated in the central portion on a lower surface, an edge area of an upper surface, a side, and an edge area of the lower surface of the substrate can be effectively removed.

摘要翻译： 一种等离子体处理装置，包括：室; 设置在所述室的上部的绝缘构件; 形成在所述室的侧壁处的接地电极，将地电位施加到所述接地电极; 以及设置在所述室的下部的下部电极，在所述下部电极上配置有基板，其中，所述下部电极被分割为多个电极。 根据本发明的一个方面，可以有效地除去积聚在基板的下表面的中心部分，上表面的边缘区域，侧面和边缘区域中的颗粒。

公开(公告)号：US20070291553A1

公开(公告)日：2007-12-20

申请号：US11755165

申请日：2007-05-30

申请人： Sung-Ryul Kim

发明人： Sung-Ryul Kim

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1051 ,  G11C7/1012 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

摘要： A data output circuit for an integrated circuit memory device includes a control circuit that is configured to generate a plurality of clock signals responsive to at least a portion of a memory column address, and a multiplexer circuit that is configured to output memory data received on input terminals thereof onto an output terminal responsive to selective invocation of the plurality of clock signals. The clock signals are invoked in an order based on the at least a portion of the memory column address.

摘要翻译： 用于集成电路存储器件的数据输出电路包括一个控制电路，该控制电路被配置为响应于存储器列地址的至少一部分产生多个时钟信号;以及多路复用器电路，被配置为输出在输入端上接收的存储器数据 其端子响应于选择性地调用多个时钟信号而输出到输出端上。 基于存储器列地址的至少一部分的顺序调用时钟信号。

公开(公告)号：US07168017B2

公开(公告)日：2007-01-23

申请号：US10648086

申请日：2003-08-26

申请人： Sung-ryul Kim ,  Jong-bok Tcho ,  Woo-seop Jeong

发明人： Sung-ryul Kim ,  Jong-bok Tcho ,  Woo-seop Jeong

IPC分类号： G11C29/00

CPC分类号： G11C29/1201 ,  G11C7/1066 ,  G11C11/401 ,  G11C29/48

摘要： A memory device, such as a DDR SDRAM, may be provided in which subsets of data output circuits of the device can be selectively enabled to allow sets of data output pins to be connected in common in a testing configuration. In some embodiments, a memory device includes a plurality of data output circuits, respective ones of which are configured to receive data from respective internal data lines and respective ones of which are coupled to respective data input/output pins. The device further includes a data output control circuit operative to selectively enable subsets of the plurality of data output circuits to drive their respective corresponding data input/output pins responsive to an externally-applied control signal. The data output control circuit may be operative to selectively cause subsets of the plurality of data output circuits to present a high impedance at their respective corresponding data input/output pins. The invention may be embodied as devices and methods.

摘要翻译： 可以提供诸如DDR SDRAM的存储器件，其中可以选择性地启用器件的数据输出电路的子集，以允许在测试配置中将数据输出引脚的组合相互连接。 在一些实施例中，存储器装置包括多个数据输出电路，其中各个数据输出电路被配置为从相应的内部数据线接收数据，并且其中相应的数据输出电路被耦合到相应的数据输入/输出引脚。 该装置还包括数据输出控制电路，其可操作以响应于外部施加的控制信号选择性地使多个数据输出电路的子集驱动其相应的数据输入/输出引脚。 数据输出控制电路可以有效地选择性地使多个数据输出电路的子集在各自相应的数据输入/输出引脚上呈现高阻抗。 本发明可以体现为设备和方法。

公开(公告)号：US20060181946A1

公开(公告)日：2006-08-17

申请号：US11319247

申请日：2005-12-27

申请人： Ki-Won Park ,  Hong-Sun Hwang ,  Sung-Ryul Kim

发明人： Ki-Won Park ,  Hong-Sun Hwang ,  Sung-Ryul Kim

IPC分类号： G11C7/02

CPC分类号： G11C7/18 ,  G11C29/12005 ,  G11C29/24 ,  G11C2029/1204

摘要： A full-stress testable memory device having an open bit line architecture and a method of testing the memory device. The memory device of the invention includes dummy bit lines, and a voltage controller connected to the dummy bit lines. The voltage controller alternately provides a first variable control voltage and a second variable control voltage to the dummy bit lines during a test mode. In accordance with a method of testing the memory device, a fixed voltage is provided to the dummy bit lines of the edge sub-arrays during a normal operation mode. However, during a test mode, the fixed voltage being applied to the dummy bit line is replaced with a supply voltage and/or a ground voltage, so that all of the sub-arrays can be equally tested.

摘要翻译： 具有开放位线架构的全压力可测试存储器件和测试存储器件的方法。 本发明的存储器件包括虚拟位线和连接到虚拟位线的电压控制器。 电压控制器在测试模式期间交替地向虚拟位线提供第一可变控制电压和第二可变控制电压。 根据测试存储器件的方法，在正常操作模式期间，将固定电压提供给边缘子阵列的虚拟位线。 然而，在测试模式期间，施加到虚拟位线的固定电压被替换为电源电压和/或接地电压，使得可以对所有子阵列进行同样的测试。

公开(公告)号：US07031201B2

公开(公告)日：2006-04-18

申请号：US11005544

申请日：2004-12-06

申请人： Sung-Ryul Kim ,  Dae-Hee Jung

发明人： Sung-Ryul Kim ,  Dae-Hee Jung

IPC分类号： G11C7/00

CPC分类号： G11C7/1087 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/413 ,  G11C2207/107 ,  G11C2207/2218

摘要： An integrated circuit memory device includes a memory cell array, a plurality of data input lines configured to convey data to the memory cell array and a plurality of data output lines configured to convey data from the memory cell array. The device also includes a memory write buffer that receives write data for the memory cell array and responsively drives the data input lines, a sense amplifier and a plurality of sense amplifier input lines configured to convey data to the sense amplifier. The device further includes a selecting circuit coupled to the data input lines, to the data output lines and to the sense amplifier input lines and configured to selectively couple the data input lines to the sense amplifier input lines responsive to a control signal.

摘要翻译： 集成电路存储器件包括存储单元阵列，被配置为将数据传送到存储单元阵列的多条数据输入线以及被配置为从存储单元阵列传送数据的多条数据输出线。 该装置还包括存储器写入缓冲器，其接收存储单元阵列的写入数据并且响应地驱动数据输入线，读出放大器和多个读出放大器输入线，其被配置为将数据传送到读出放大器。 该装置还包括耦合到数据输入线，数据输出线和读出放大器输入线的选择电路，并且被配置成响应于控制信号将数据输入线选择性地耦合到读出放大器输入线。

公开(公告)号：US5986303A

公开(公告)日：1999-11-16

申请号：US911351

申请日：1997-08-07

申请人： Jong Moo Choi ,  Sung Ryul Kim ,  Young Keun Park

发明人： Jong Moo Choi ,  Sung Ryul Kim ,  Young Keun Park

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L29/66825 ,  H01L27/115

摘要： A flash memory device has improved erasable characteristics and device reliability. The flash memory device includes a semiconductor substrate and heavily doped impurity regions formed spaced apart from one another by a predetermined distance in the semiconductor substrate in a first direction. First and second isolation regions are formed spaced apart from each other by a second predetermined distance on the semiconductor substrate, in a second direction which is preferably at a right angle to the first direction. Each of the floating gates are formed between the first and second isolation regons and between the heavily doped impurity regions. The control gate lines are formed between the first and second isolation regions, and over the floating gates in the same direction as the first and second isolation regions. An erase gate line is formed to have a narrower width than the floating gate, and is formed over the floating gate, preferably at a right angle to the control gate line.

摘要翻译： 闪存器件具有改进的可擦除特性和器件可靠性。 闪速存储器件包括在第一方向上在半导体衬底中彼此间隔开预定距离形成的半导体衬底和重掺杂杂质区。 第一隔离区域和第二隔离区域在第二方向上在半导体衬底上彼此间隔开第二预定距离，优选地与第一方向成直角。 每个浮置栅极形成在第一和第二隔离晶体之间以及重掺杂杂质区之间。 控制栅极线形成在第一和第二隔离区域之间，并且在与第一和第二隔离区域相同的方向上在浮动栅极上形成。 擦除栅极线形成为具有比浮动栅极窄的宽度，并且形成在浮动栅极上，优选地与控制栅极线成直角。