公开(公告)号：US08492221B2

公开(公告)日：2013-07-23

申请号：US13433282

申请日：2012-03-28

Applicant: Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Chia-Hao Chang

Inventor： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Chia-Hao Chang

IPC: H01L21/8242

CPC classification number: H01L29/7813 ,  H01L29/0653 ,  H01L29/0886 ,  H01L29/456 ,  H01L29/66734

Abstract: A method for fabricating a power semiconductor device is provided. A substrate with a first conductivity type is prepared. A semiconductor layer with a second conductivity type is formed on the substrate. A hard mask pattern having at least an opening is formed on the semiconductor layer. A first trench etching is performed to form a first recess in the semiconductor layer via the opening. A first ion implantation is performed to vertically implant dopants into the bottom of the first recess via the opening, thereby forming a first doping region. A second trench etching is performed to etch through the first doping region, thereby forming a second recess.

Abstract translation: 提供一种制造功率半导体器件的方法。 制备具有第一导电类型的衬底。 在基板上形成具有第二导电类型的半导体层。 在半导体层上形成至少具有开口的硬掩模图案。 执行第一沟槽蚀刻以经由开口在半导体层中形成第一凹槽。 执行第一离子注入以通过开口垂直地将掺杂剂注入第一凹槽的底部，从而形成第一掺杂区域。 执行第二沟槽蚀刻以蚀刻穿过第一掺杂区域，从而形成第二凹槽。

公开(公告)号：US20130134487A1

公开(公告)日：2013-05-30

申请号：US13541763

申请日：2012-07-04

Applicant: Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Chia-Hao Chang

Inventor： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Chia-Hao Chang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/66712

Abstract: The present invention provides a power transistor device with a super junction including a substrate, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The first epitaxial layer is disposed on the substrate, and has a plurality of trenches. The trenches are filled up with the second epitaxial layer, and a top surface of the second epitaxial layer is higher than a top surface of the first epitaxial layer. The second epitaxial layer has a plurality of through holes penetrating through the second epitaxial layer and disposed on the first epitaxial layer. The second epitaxial layer and the first epitaxial layer have different conductivity types. The through holes are filled up with the third epitaxial layer, and the third epitaxial layer is in contact with the first epitaxial layer. The third epitaxial layer and the first epitaxial layer have the same conductivity type.

Abstract translation: 本发明提供一种功率晶体管器件，其具有包含衬底，第一外延层，第二外延层和第三外延层的超结的超级结。 第一外延层设置在基板上，并且具有多个沟槽。 沟槽被第二外延层填充，并且第二外延层的顶表面高于第一外延层的顶表面。 第二外延层具有穿过第二外延层并设置在第一外延层上的多个通孔。 第二外延层和第一外延层具有不同的导电类型。 通孔用第三外延层填充，第三外延层与第一外延层接触。 第三外延层和第一外延层具有相同的导电类型。

公开(公告)号：US08404531B2

公开(公告)日：2013-03-26

申请号：US13349038

申请日：2012-01-12

Applicant: Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Yi-Chun Shih ,  Main-Gwo Chen

Inventor： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Yi-Chun Shih ,  Main-Gwo Chen

IPC: H01L21/337

CPC classification number: H01L29/7802 ,  H01L21/2253 ,  H01L21/2255 ,  H01L29/0634 ,  H01L29/1095

Abstract: A method for fabricating a power transistor includes: (a) forming a trench in a substrate with a first electrical type; (b) diffusing second electrical type carriers into the substrate from the trench such that the substrate is formed into a first part and a second part that is diffused with the second electrical type carriers and that adjoins the trench, the first and second parts being crystal lattice continuous to each other; (c) forming a filling portion in the trench, the filling portion adjoining the second part; (d) performing a carrier-implanting process in the second part and the filling portion; and (e) forming over the substrate a gate structure that has a dielectric layer and a conductive layer.

Abstract translation: 一种制造功率晶体管的方法包括：（a）在第一电气类型的衬底中形成沟槽; （b）从沟槽将第二电型载体扩散到衬底中，使得衬底形成为第一部分，第二部分与第二电气型载流子扩散并邻接沟槽，第一和第二部分是晶体 格子相互连续; （c）在所述沟槽中形成填充部分，所述填充部分邻接所述第二部分; （d）在第二部分和填充部分中执行载体植入过程; 和（e）在衬底上形成具有电介质层和导电层的栅极结构。

公开(公告)号：US20120295410A1

公开(公告)日：2012-11-22

申请号：US13234132

申请日：2011-09-15

Applicant: Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

Inventor： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

IPC: H01L21/336

CPC classification number: H01L29/66666 ,  H01L21/2255 ,  H01L21/2256 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/7811 ,  H01L29/7813

Abstract: A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer.

Abstract translation: 用于制造具有减小的米勒电容的超结半导体功率器件的方法包括以下步骤。 提供了N型衬底，并且在N型衬底上形成P型外延层。 至少在P型外延层中形成沟槽，随后在沟槽的内表面上形成缓冲层。 将N型掺杂剂层填充到沟槽中，然后蚀刻N型掺杂剂层以在沟槽的上部形成凹陷结构。 形成栅极氧化层，同时，N型掺杂剂层中的掺杂剂扩散到P型外延层中，形成N型扩散层。 最后，将栅极导体填充到凹陷结构中，并且在P型外延层中的栅极导体周围形成N型源极掺杂区。

公开(公告)号：US20120276726A1

公开(公告)日：2012-11-01

申请号：US13211304

申请日：2011-08-17

Applicant: Yung-Fa Lin ,  Shou-Yi Hsu ,  Yi-Lin Sun

Inventor： Yung-Fa Lin ,  Shou-Yi Hsu ,  Yi-Lin Sun

IPC: H01L21/225

CPC classification number: H01L21/2257 ,  H01L29/04 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7811

Abstract: A method for fabricating a semiconductor power device includes the following steps. First, a substrate having thereon at least a semiconductor layer and a pad layer is provided. Then, at least a trench is etched into the pad layer and the semiconductor layer followed by depositing a dopant source layer in the trench and on the pad layer. A process is carried out thermally driving in dopants of the dopant source layer into the semiconductor layer. A rapid thermal process is performed to mend defects in the dopant source layer and defects between the dopant source layer and the semiconductor layer. Finally, a polishing process is performed to remove the dopant source layer from a surface of the pad layer.

Abstract translation: 一种制造半导体功率器件的方法包括以下步骤。 首先，提供其上具有至少半导体层和衬垫层的衬底。 然后，将至少一个沟槽蚀刻到衬垫层和半导体层中，随后在沟槽和衬垫层中沉积掺杂剂源层。 对掺杂剂源层的掺杂剂进行半导体层的热驱动。 进行快速热处理以修补掺杂剂源层中的缺陷和掺杂剂源层和半导体层之间的缺陷。 最后，进行抛光处理以从衬垫层的表面去除掺杂剂源层。

公开(公告)号：US08242034B2

公开(公告)日：2012-08-14

申请号：US12940716

申请日：2010-11-05

Applicant: Yung-Fa Lin ,  Te-Chun Wang

Inventor： Yung-Fa Lin ,  Te-Chun Wang

IPC: H01L47/00

CPC classification number: H01L45/126 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16

Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer.

Abstract translation: 提供了相变存储器件及其制造方法。 相变存储器件的示例性实施例包括形成在衬底上的底部电极。 在底部电极上方形成第一电介质层。 加热电极形成在第一电介质层中并且部分地突出在第一电介质层上，其中加热电极包括嵌入在第一电介质层内的本征部分，堆叠在本征部分上的还原部分和围绕侧壁的氧化物间隔物 的减少部分。 在第一电介质层上形成相变材料层并覆盖加热电极，相变材料层接触加热电极的减少部分的顶表面。 顶部电极形成在相变材料层上并与相变材料层接触。

公开(公告)号：US20110053333A1

公开(公告)日：2011-03-03

申请号：US12940716

申请日：2010-11-05

Applicant: Yung-Fa Lin ,  Te-Chun Wang

Inventor： Yung-Fa Lin ,  Te-Chun Wang

IPC: H01L21/02

CPC classification number: H01L45/126 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16

Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer.

Abstract translation: 提供了相变存储器件及其制造方法。 相变存储器件的示例性实施例包括形成在衬底上的底部电极。 在底部电极上方形成第一电介质层。 加热电极形成在第一电介质层中并且部分地突出在第一电介质层上，其中加热电极包括嵌入在第一电介质层内的本征部分，堆叠在本征部分上的还原部分和围绕侧壁的氧化物间隔物 的减少部分。 在第一电介质层上形成相变材料层并覆盖加热电极，相变材料层接触加热电极的减少部分的顶表面。 顶部电极形成在相变材料层上并与相变材料层接触。

公开(公告)号：US07858961B2

公开(公告)日：2010-12-28

申请号：US12325067

申请日：2008-11-28

Applicant: Jen-Chi Chuang ,  Yung-Fa Lin ,  Ming-Jeng Huang

Inventor： Jen-Chi Chuang ,  Yung-Fa Lin ,  Ming-Jeng Huang

IPC: H01L47/00

CPC classification number: H01L45/144 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/126 ,  H01L45/148 ,  H01L45/1691

Abstract: An exemplary phase change memory device is provided, including a substrate with a first electrode formed thereover. A first dielectric layer is formed over the first electrode and the substrate. A plurality of cup-shaped heating electrodes is respectively disposed in a portion of the first dielectric layer. A first insulating layer is formed over the first dielectric layer, partially covering the cup-shaped heating electrodes and the first dielectric layer therebetween. A second insulating layer is formed over the first dielectric layer, partially covering the cup-shaped heating electrodes and the first dielectric layer therebetween. A pair of phase change material layers is respectively disposed on opposing sidewalls of the second insulating layer and contacting with one of the cup-shaped heating electrodes. A pair of first conductive layers is formed on the second insulating layer along the second direction, respectively.

Abstract translation: 提供了一种示例性相变存储器件，包括其上形成有第一电极的衬底。 第一电介质层形成在第一电极和衬底之上。 多个杯形加热电极分别设置在第一电介质层的一部分中。 在第一电介质层上形成第一绝缘层，部分覆盖杯形加热电极和第一绝缘层之间的第一介电层。 在第一电介质层上形成第二绝缘层，部分地覆盖杯状加热电极和第一绝缘层。 一对相变材料层分别设置在第二绝缘层的相对的侧壁上并与杯形加热电极之一接触。 一对第一导电层分别沿第二方向形成在第二绝缘层上。

公开(公告)号：US07855378B2

公开(公告)日：2010-12-21

申请号：US11836093

申请日：2007-08-08

Applicant: Yung-Fa Lin ,  Te-Chun Wang

Inventor： Yung-Fa Lin ,  Te-Chun Wang

IPC: H01L47/00

CPC classification number: H01L45/126 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16

Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer.

Abstract translation: 提供了相变存储器件及其制造方法。 相变存储器件的示例性实施例包括形成在衬底上的底部电极。 在底部电极上方形成第一电介质层。 加热电极形成在第一电介质层中并且部分地突出在第一电介质层上，其中加热电极包括嵌入在第一电介质层内的本征部分，堆叠在本征部分上的还原部分和围绕侧壁的氧化物间隔物 的减少部分。 在第一电介质层上形成相变材料层并覆盖加热电极，相变材料层接触加热电极的减少部分的顶表面。 顶部电极形成在相变材料层上并与相变材料层接触。

公开(公告)号：US20090008621A1

公开(公告)日：2009-01-08

申请号：US11966584

申请日：2007-12-28

Applicant: Yung-Fa Lin ,  Te-Chun Wang

Inventor： Yung-Fa Lin ,  Te-Chun Wang

IPC: H01L45/00

CPC classification number: H01L45/1233 ,  H01L45/06 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

Abstract: A phase-change memory element is provided. The phase-change memory element of an embodiment of the invention comprises a phase-change material layer with a concave, and a heater with an extended part, wherein the extended part of the heater is wedged in the concave of the phase-change material layer. Specifically, the extended part of the heater has a length of 10˜5000 Å.

Abstract translation: 提供了相变存储元件。 本发明的实施例的相变存储元件包括具有凹部的相变材料层和具有延伸部分的加热器，其中加热器的延伸部分楔入相变材料层的凹部 。 具体来说，加热器的延伸部分的长度为10〜5000。